Loren,
The Intel way of handling write combine can be found in the
following application note:
http://www.intel.com/design/pentiumii/applnots/24442201.pdf
and also at Chapter 10 of Volume 3 of the IA32 Architecture
Software Developer’s Manual. You can find it at
http://www.intel.com/design/Pentium4/documentation.htm#manuals
If I’m not wrong, Pentium processors P4, P6, Xeon and M support
write combining by setting bits in the Memory’s MTRR and also on
the PAT if you have one. The PAT actually overrides the
selections you make in your MTRR(s). Note also that WC is a
caching strategy, and information comes lumped in the sections
about cache management and control.
You can read section 10.11 of that manual to see all the details
about MTRRs and about the PAT. The PAT is driven by page table
bits, so you can control things at a higher level by fiddling
with the PAT, PCD and PWT bits of your page tables.
You can test if a processor supports MTRRs by issuing a CPUID
instruction and testing bit 12 of edx. The presence of a PAT is
indicated by bit 16 of the same register. You should then test
bit 10 of the MTRRCAP register to make sure that write combining
is supported. Finally, you must access the MTRR(s) of the memory
region(s) you want to enable or disable write combining and flip
the bit(s) accordingly, and/or set the PAT accordingly to your
needs.
It’s not for the fainthearted, but we graphics driver writers
are anything but! And you know, it helps to have a scope or a
VMetro to debug it when the doo hits the fan.
This is all kind of rusty in my mind, and I may have forgotten
something or made some mistake in the above writing, but, hope
this helps,
Alberto.