TSC-deadline timer in windows

NTDEV
1

Hi,
I’ve been experimenting with TSC-Deadline mode for per-CPU timing, and it gives remarkable precision and stability — especially noticeable in games and real-time workloads. My logs look like:

00000033 16.32992554 [APIC] TSC-Deadline supported: 1
00000034 16.32994461 [APIC] CPU 0: TSC-Deadline mode, deadline=0x4058e9df54
00000035 16.32998085 [APIC] CPU 1: TSC-Deadline mode, deadline=0x4058ec047f
00000036 16.33001518 [APIC] CPU 2: TSC-Deadline mode, deadline=0x4058ee3ec7
00000037 16.33005333 [APIC] CPU 3: TSC-Deadline mode, deadline=0x4058f07347
00000038 16.33009148 [APIC] CPU 4: TSC-Deadline mode, deadline=0x4058f2d7b2
00000039 16.33012772 [APIC] CPU 5: TSC-Deadline mode, deadline=0x4058f51c7d
00000040 16.33017349 [APIC] CPU 6: TSC-Deadline mode, deadline=0x4058f7c3c6
00000041 16.33020782 [APIC] CPU 7: TSC-Deadline mode, deadline=0x4058f9ece2 i trigger it by hooking interrupt service routine is this the fastest we can go on windows ?

2

00000003 0.04636210 [HPET] Successfully mapped HPET at virtual address 0xFFFF830188F74000
00000004 0.04638190 [HPET] Counter period: 69841279 femtoseconds (14.318 MHz)
00000005 0.04708510 [TSC] Calibration results:
00000006 0.04708680 [TSC] HPET delta: 10000 ticks
00000007 0.04708800 [TSC] TSC delta: 2795904 cycles
00000008 0.04708950 [TSC] Calibrated TSC frequency: 4003230185 Hz (4.003 GHz)
00000009 0.04709090 [TSC] Timer interval set to 4003230 cycles (1ms)
00000010 0.04712370 [TSC] CPU 0: Timer armed, deadline=0xde21cf9a23a6
00000011 0.04715600 [TSC] CPU 1: Timer armed, deadline=0xde21cf9c22a5
00000012 0.04718760 [TSC] CPU 2: Timer armed, deadline=0xde21cf9e11a2
00000013 0.04722220 [TSC] CPU 3: Timer armed, deadline=0xde21cfa03162
00000014 0.04726240 [TSC] CPU 4: Timer armed, deadline=0xde21cfa2ae4b
00000015 0.04730660 [TSC] CPU 5: Timer armed, deadline=0xde21cfa556ad
00000016 0.04734430 [TSC] CPU 6: Timer armed, deadline=0xde21cfa7a61c
00000017 0.04738260 [TSC] CPU 7: Timer armed, deadline=0xde21cfa9fd52

calibrate with HPET