Regarding ISR in UART

OSR_Community_User · October 24, 2001, 11:54am

Hi,
I am facing a problem when i write to a UART.

I am using the microsoft serial driver sample
which comes along with windows 2000 ddk as baseline
and modifying it to suit our requirements.

When i get any data from the application, i
finish the initial processing of data, like locking
pages and set the write length and buffer pointer in
the serial device extension. Then i toggle the
interrupt line, so that my ISR will take over and take
care of sending the data.

Once all the bytes are sent the ISR will schedule
a DPC in which i complete the IO request.

The FIFO size is 14 bytes.

When i submit 20 bytes of data and toggle the
interrupt line, the ISR takes control immediately and
sends 14 bytes. The ISR doesn’t get control for about
80 seconds after it had sent sent first 14 bytes.

After 80 seconds the ISR gets control and sends
the rest of 6 bytes. I couldn’t understand why so much
delay is encountered.

Any help would be appreciated. Thanks in advance.

With Regards
D.Nagarajan.

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OSR_Community_User · October 24, 2001, 1:03pm

Are you disabling the interrupts on the device? If you are, are you enabling
them again, and a system timeout is then enabling them for you. I really
suspect this is the case since you indicate that you toggle interrupts at
the start and your ISR is called. On a serial device you generally don’t
need to do that. Hell, I have a fibre channel device running at 1.02
gigabits per second and I don’t disable the devices interrupts. On an RS-485
comport running at 100K bps I didn’t disable the devices interrupts, and
that only had a 4 byte FIFO. Bottom line, I think you disabled the devices
interrupt line and then did NOT enable it.

Here is how I handled the transmit side of that 100K com line —

I created a ring buffer with a store and fetch index and a proper spinlock.
When data came in from the app I copied it into the ring buffer, updated the
store index, and toggled the interrupt line. The ISR called the transmit
logic which entered a for loop and started transmitting characters and
updating the fetch index until either there was no more data or the device
set its “NO MORE”. Once I was out of the transmit loop I checked to see if
the ring buffer was empty (store == fetch), queued a DPC to complete the
associated IRP if it was empty, and returned form the ISR with a TRUE. When
that FIFO interrupt triggers on FIFO empty, the ISR gets called again, if
store > fetch, and I do all that again. At no time do I disable/enable
device interrupts.

Gary G. Little
Staff Engineer
Broadband Storage, Inc.
xxxxx@broadstor.com

-----Original Message-----
From: Nagarajan Duraisamy [mailto:xxxxx@yahoo.com]
Sent: Wednesday, October 24, 2001 8:52 AM
To: NT Developers Interest List
Subject: [ntdev] Regarding ISR in UART