Hi All,
I’m trying to find out if there’s any way to do the following - we have a
PCI express device that we’re trying to assign I/O resources in the 0x200 -
0x3ff range (length 8) via our installation driver - this requirement is due
to existing customers desire to use their own legacy type driver which use
hard coded I/O. I am able to alter the resources in the
IRP_MN_FILTER_RESOURCE_REQUIREMENTS dispatch routine but it only lets me put
it anywhere in the 0x1000-0x1fff range.
I understand that this is due to the PCI express root controller being
assigned that range and thus it looks like there’s no way to get anything
below 0x1000 assigned to my device as I’ve read in
http://www.microsoft.com/whdc/system/bus/PCI/pcibridge-cardbus.mspx
http: :
“the remainder of free I/O space in the first 4 KB can be allocated to other
devices, but it cannot be allocated to PCI-to-PCI bridges…” and later in
the article it reads “… root ports in the root complex…are presented as
virtual PCI-to-PCI bridges”.
So I’m looking for if someone in this news group might know of a way around
this.
Thanks
Tim</http:>
Tim Gobeli wrote:
I’m trying to find out if there’s any way to do the following – we
have a PCI express device that we’re trying to assign I/O resources in
the 0x200 - 0x3ff range (length 8) via our installation driver – this
requirement is due to existing customers desire to use their own
legacy type driver which use hard coded I/O. I am able to alter the
resources in the IRP_MN_FILTER_RESOURCE_REQUIREMENTS dispatch routine
but it only lets me put it anywhere in the 0x1000-0x1fff range.
…
So I’m looking for if someone in this news group might know of a way
around this.
Why would you try for a software solution to this? Even if you change
IRP_MN_FILTER_RESOURCE_REQUIREMENTS, that doesn’t alter the BARs in
configuration space, so it won’t route the I/O port requests to your device.
Why don’t you just modify your device’s PCI configuration space to claim
that range in its BARs?
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
You’d have to use a LOGCONFIG (??) section in your INF, and given this really is not a legacy (ISA), the chances are it just might not work. Not to mention that once you do that you basicalyy bolox power management.
Tim’s got the best idea … since you control the hardware, change the BARS.
–
The personal opinion of
Gary G. Little
“Tim Gobeli” wrote in message news:xxxxx@ntdev…
Hi All,
I’m trying to find out if there’s any way to do the following - we have a PCI express device that we’re trying to assign I/O resources in the 0x200 - 0x3ff range (length 8) via our installation driver - this requirement is due to existing customers desire to use their own legacy type driver which use hard coded I/O. I am able to alter the resources in the IRP_MN_FILTER_RESOURCE_REQUIREMENTS dispatch routine but it only lets me put it anywhere in the 0x1000-0x1fff range.
I understand that this is due to the PCI express root controller being assigned that range and thus it looks like there’s no way to get anything below 0x1000 assigned to my device as I’ve read in http://www.microsoft.com/whdc/system/bus/PCI/pcibridge-cardbus.mspx :
“the remainder of free I/O space in the first 4 KB can be allocated to other devices, but it cannot be allocated to PCI-to-PCI bridges.” and later in the article it reads “. root ports in the root complex…are presented as virtual PCI-to-PCI bridges”.
So I’m looking for if someone in this news group might know of a way around this.
Thanks
Tim
There’s no way to do this. The chipset hardware prevents it. All PCI Express devices live beneath a Root Port. A root port only passes I/O transactions from its primary to secondary side if the address is within its I/O window (I/O base/limit registers in the PCI-PCI bridge representing the root port), so even if a BAR is programmed to this address the accesses to it will not make it to your device unless the I/O window also covers the same range. I/O windows have 0x1000 byte granularity, so to do this you would have to get 0-0x1000 programmed into the root port. This range will conflict with a host of legacy devices in the south bridge, and therefore can’t be allocated to the root port.
Even if you could convince Windows to allocate the range to the root port, you would probably find that the chipset is built to either a) generate bus errors due to the conflicting address decoding between the root port and the southbridge devices, or b) forward transactions in this range directly to the south bridge regardless of the root port I/O window setting, under the assumption that these addresses are for devices down there.
Old school PCI had the concept of a subtractive decode bridge, which could be used to allow unused legacy addresses to flow down one path. But PCI Express didn’t add this concept.
I am pretty sure this is a fundamental hardware problem that can’t be worked around.
Dave
>>>>>>
modify your device’s PCI configuration space to claim
that range in its BARs
<<<<<<
How?
If the device is on the secondary side of a bridge, the bridge is only
going to forward what’s between the bridge’s IOBase and IOLimit registers.
Unless we’re talking about a bridgte with the VGA Enable bit set in the
Bridge Control register, and then we’re only talking about 3B0-3BB and
3C0-3DF, which are probably in use by the VGA controller. And that bit
won’t be set unless there is a VGA device on the other side of the bridge.
Tim Roberts
Sent by: xxxxx@lists.osr.com
06/29/2007 02:55 PM
Please respond to
“Windows System Software Devs Interest List”
To
“Windows System Software Devs Interest List”
cc
Subject
Re: [ntdev] Reassigning PCI Express I/O resources
Tim Gobeli wrote:
>
>
>
> I?m trying to find out if there?s any way to do the following ? we
> have a PCI express device that we?re trying to assign I/O resources in
> the 0x200 - 0x3ff range (length 8) via our installation driver ? this
> requirement is due to existing customers desire to use their own
> legacy type driver which use hard coded I/O. I am able to alter the
> resources in the IRP_MN_FILTER_RESOURCE_REQUIREMENTS dispatch routine
> but it only lets me put it anywhere in the 0x1000-0x1fff range.
>
> …
>
> So I?m looking for if someone in this news group might know of a way
> around this.
>
Why would you try for a software solution to this? Even if you change
IRP_MN_FILTER_RESOURCE_REQUIREMENTS, that doesn’t alter the BARs in
configuration space, so it won’t route the I/O port requests to your
device.
Why don’t you just modify your device’s PCI configuration space to claim
that range in its BARs?
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
—
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Thanks Dave - that’s the answer I was looking for - whetherit could or could not be done, I guess the only other thing is could a Laptop have a differrent archetecture to where there might only be a primary bus that’s pci express and allows this address range - we’ve seen some different things on laptops and are getting one in with the expresss slot and (since this is what the customer actually is going to be using) we’re hoping that might be the case (although I’m pretty doubtful)
Tim,
Nope. The existence of root ports is mandatory in PCIe, and subtractive decode is not part of the transaction protocol at all. Nothing about this will change on laptops, I don’t believe.
Dave