READ_REGISTER_ULONG return 0xFFFFFFFF on W7 64bit PCIe kmdf driver

NTDEV
1

Dear all,

we have the same problem reported by Jeffry Gummeson in this thread: http://www.osronline.com/ShowThread.cfm?link=156668

except that we are developing a kwdf driver for W7 64 bit.

We are testing interrupt based DMA transfers using a board with a Xilinx FPGA (Virtex 6) acting as PCI Express Endpoint. We use the IP core Integrated Block for PCI Express provided by Xilinx.

In our PC the negotiated maximum payload size for TLP is 128 Bytes.

If we set the TLP payload size to 128 Bytes and the DMA transfer size (from board to PC RAM) to a multiple of TLP payload size, everithing work as expected.

When we set an arbitrary TLP ps (e.g. 124 Bytes), even if the DMA transfer size is a multiple of TLP ps, we observe only a few successful transfers and then the PCI Configuration Space of our board seems to disappear (as confirmed with the kd !pci return "0xFFFFFFFF bogus skipping rest of device … ").

From the board side we still receive and correctly handle READ_REGISTER_ULONG command (corresponding to an MRd TLP followed by a CplD TLP sent by our board to the rc) but from the driver side we read 0xFFFFFFFF.

Additionally, after a few attempts to debug a READ_REGISTER_ULONG instruction via kd the PC hangs freezing (no BSOD).

We are aware of:

  • 4KB boundary requirement for memory transfer
  • correct handle of 32 or 64 bit TLP addressing required for memory transfers below or beyond 4GB

Any ideas on what are the causes of this problem?

Thanks,
Aurelio

2

My first inclination would be to say “hardware problem?”

What have you done to diagnose this at the hardware level?

Got it on a bus analyzer? Used an on-chip diag function (like ChipScope in your Xilinx device)?

Peter
OSR

3

xxxxx@gmail.com wrote:

When we set an arbitrary TLP ps (e.g. 124 Bytes), even if the DMA transfer size is a multiple of TLP ps, we observe only a few successful transfers and then the PCI Configuration Space of our board seems to disappear (as confirmed with the kd !pci return "0xFFFFFFFF bogus skipping rest of device … ").

I’m not sure what you mean by “set an arbitrary TLP ps”. The maximum
TLP size is set by the BIOS, and you don’t get to modify that. The only
possible choices are 128, 256, and 512.

Are you talking about setting an arbitrary limit register somewhere
within your PCI Express IP? Why would you do that? There’s no point.

Many PCI Express DMA engines have trouble with misaligned data. I think
this arises because many memory interfaces work in units of 32 bytes or
64 bytes, and when people design FIFOs to cross between them, they do
the byte lane shifting incorrectly.

–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.