Re: posible bug in XP kernel - was MmMapLockedPages.. . on XP vs. 2000

Actually I think it is the cached writers who are the problem, not the
non-cached writers. The non-cached write to memory will indeed invalidate
the cache lines of the cached writer cpus, due to memory bus snooping,
however the cached writers will not invalidate the cache lines of the
non-cached writer, 'cause he ain’t using the cache. The cpus using cache
will have a coherent view, the cpu(s) doing non-cached access may not.
Particularly a problem if invalidates can be statisfied from cache rather
than from memory.

-----Original Message-----
From: Maxim S. Shatskih [mailto:xxxxx@storagecraft.com]
Sent: Friday, June 21, 2002 10:53 AM
To: NT Developers Interest List
Subject: [ntdev] Re: posible bug in XP kernel - was
MmMapLockedPages… . on XP vs. 2000

> everywhere, but can somebody explain exactly how the cache
coherency
> protocol gets violated in this case and memory access gets
potentially
> incoherent?

Imagine the same page double-mapped to the address space by 2
different PTEs, one with caching on, other with caching off.
Now imagine some code writes a value via noncached PTE. The
value is updated in memory and not updated in the cache. The
read from cached PTE will read the stale value.

This is a good old problem which is known to people working
on hardware which requires the software to know on cache
coherency issues (i.e. PowerPC).

Max


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