xxxxx@sneakemail.com said:
The data was burst as 6 writes (actually, it first became a burst of 3
64-bit writes across a 64-bit cPCI backplane, which was then converted
back to 6 32-bit writes by the 64-bit to 32-bit PCI-PCI bridge on the
PMC carrier where the device was installed).
There is a good chance that PCI-to-PCI are doing the write combining.
They are allowed, in certain cases.
Still a slave read is tons more expensive then a bus mastered write.
Even at RS232 speeds, you would really rather the device did bus-
mastered writes then target reads. To the original point, you would
have to look far and wide to find a case where you would really rather
do PIO (in the form, inevitably, of reads) instead of DMA bus mastered
writes.
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