RE: Newbie question: What are map registers really ..- .

Many Thanks for your quick response.

That’s a terrible truth. How can I avoid additional copying data by kernel
DMA support? By specifying only one map register during call to
AllocateAdapterChannel? Or in calling ‘GetScatterGatherList’ instead of
‘AllocateAdapterChannel’ and subsequently emulating scatter/gather
capabilities by a staged transfer driven by interrupt routine? Or lastly by
skipping kernel DMA support?

-----Original Message-----
From: Roddy, Mark [mailto:xxxxx@stratus.com]
Sent: Tuesday, February 06, 2001 5:51 PM
To: NT Developers Interest List
Subject: [ntdev] RE: Newbie question: What are map registers
really …

Map registers on standard x86 platforms are implemented as
non-paged pool
with a physical address less than 64MB. The OS allocates ‘map
registers’ in
this region in physically contiguous chunks of 4K pages to
support ISA(and
other) busses that cannot address the full 32-bit physical
address space,
and to support non-scatter/gather busmaster devices even if
they are on a
bus (e.g. pci) that does support the full 32-bit physical
address space.
Data is simply copied in and out of the ‘map registers’ as part of the
kernels managed DMA support.

Other platforms may actually have hardware map registers (NT4
on Alpha.)

Mark Roddy
xxxxx@hollistech.com
www.hollistech.com
WindowsNT Windows 2000 Consulting Services

> -----Original Message-----
> From: Moebius, V. [mailto:xxxxx@baslerweb.com]
> Sent: Tuesday, February 06, 2001 10:24 AM
> To: NT Developers Interest List
> Subject: [ntdev] Newbie question: What are map registers really …
>
>
> I perform a staged PCI (32bit) bus master DMA transfer under
> W2K on an Intel
> platform with a page size of 4k.
> I heard there are no map registers on Intel platforms.
> Therefore I expected
> that DMA would take place in 4k stages. But during debugging
> I found that
> there is a number of 2 map registers available on my test
system (with
> register base != NULL) and DMA is successfully performed in
8k stages.
> What kind of mechanics implements map registers on Intel
> platforms? How does
> it work?
>
> Thanks in advance,
>
> Volker Moebius
> Basler AG
> http://www.baslerweb.com
>
> —
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