RE: IO vs memory mapping

NTDEV
1

I just want some explanation between I/O address and I/O-memory mapping.
I’m so confused about that.

If the I/O registers are mapped in the main memory, the driver must
access to this memory address to read or write to these registers? So,
does the peripheral will know about this change?

I think that I understand about I/O address space. Someone correct me if
I’m not right, the architecture (i.e. processor) can support I/O and
memory space, and also the system can be mapped only in the memory
space. It depends which architecture we are using. The processor sends
the address to the address line, some control signals are used to select
between I/O, memory (M/IO, Rd, Wr).

But, if the processor supports only memory space, I presume that there
is no M/IO signal. In addition, the peripherals have I/O decoders and
memory decoders. I don’t understand how access to I/O registers if the
processor supports only the memory space.

The MmMapIoSpace function is useful to map IO address space to memory
space? I don’t understand how the memory address can access to the IO
register.

I hope to get some answers about this topic.

Regards

Christian

2

Have a long talk with an EE. Devices are designed at the hardware level for
port IO or memory mapped IO. Some CPUs don’t support one or the other, but
the Intel i386 does support both.

“Christian Grenier” wrote in message
news:xxxxx@ntdev…
>
> I just want some explanation between I/O address and I/O-memory mapping.
> I’m so confused about that.
>
>
> If the I/O registers are mapped in the main memory, the driver must
> access to this memory address to read or write to these registers? So,
> does the peripheral will know about this change?
>
> I think that I understand about I/O address space. Someone correct me if
> I’m not right, the architecture (i.e. processor) can support I/O and
> memory space, and also the system can be mapped only in the memory
> space. It depends which architecture we are using. The processor sends
> the address to the address line, some control signals are used to select
> between I/O, memory (M/IO, Rd, Wr).
>
> But, if the processor supports only memory space, I presume that there
> is no M/IO signal. In addition, the peripherals have I/O decoders and
> memory decoders. I don’t understand how access to I/O registers if the
> processor supports only the memory space.
>
> The MmMapIoSpace function is useful to map IO address space to memory
> space? I don’t understand how the memory address can access to the IO
> register.
>
> I hope to get some answers about this topic.
>
> Regards
>
> Christian
>
>
>
>
>

3

On PCI and ISA, device registers can be accessed using memory or IO (in/out) instructions. The decoding of the registers is done by the BAR registers in the device, which are setup using PCI configuration cycles. A BAR register is explicitly declared by the h/w as an IO or a Memory address decode but not both.

If the BAR is a memory bar, then the address stored in the BAR is a physical address.

MmMapIoSpace is used to obtain a virtual address that maps an underlying physical memory address range. This could be real ram memory or device registers depending on the physical address range that is passed. Typically, device registers are accessed non-cached (see the third parameter to MmMapIoSpace). The exception is video memory which performs best with write-combining.

On ISA, the address and data buses were separate, but a separate control line was used to indicate a memory or IO transfer. On PCI the address and data share the same signal lines, additional control signals indicate the type of transfer that is occurring. For IO operations, the address is the DX register value for the corresponding in or out instruction. For Memory Mapped operations, the address is obtained from the specified memory reference in the instruction (which could be a variety of different instructions).

Duane.

-----Original Message-----
From: David J. Craig [mailto:xxxxx@yoshimuni.com]
Sent: Wednesday, October 15, 2003 1:01 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] Re: IO vs memory mapping

Have a long talk with an EE. Devices are designed at the hardware level for
port IO or memory mapped IO. Some CPUs don’t support one or the other, but
the Intel i386 does support both.

“Christian Grenier” wrote in message
news:xxxxx@ntdev…
>
> I just want some explanation between I/O address and I/O-memory mapping.
> I’m so confused about that.
>
>
> If the I/O registers are mapped in the main memory, the driver must
> access to this memory address to read or write to these registers? So,
> does the peripheral will know about this change?
>
> I think that I understand about I/O address space. Someone correct me if
> I’m not right, the architecture (i.e. processor) can support I/O and
> memory space, and also the system can be mapped only in the memory
> space. It depends which architecture we are using. The processor sends
> the address to the address line, some control signals are used to select
> between I/O, memory (M/IO, Rd, Wr).
>
> But, if the processor supports only memory space, I presume that there
> is no M/IO signal. In addition, the peripherals have I/O decoders and
> memory decoders. I don’t understand how access to I/O registers if the
> processor supports only the memory space.
>
> The MmMapIoSpace function is useful to map IO address space to memory
> space? I don’t understand how the memory address can access to the IO
> register.
>
> I hope to get some answers about this topic.
>
> Regards
>
> Christian
>
>
>
>
>

—
Questions? First check the Kernel Driver FAQ at http://www.osronline.com/article.cfm?id=256

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4

That’s a lot of questions! I’ve added some comments in line below.

=====================
Mark Roddy

-----Original Message-----
From: Christian Grenier [mailto:xxxxx@mcdi.com]
Sent: Wednesday, October 15, 2003 12:56 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

I just want some explanation between I/O address and
I/O-memory mapping. I’m so confused about that.

If the I/O registers are mapped in the main memory, the
driver must access to this memory address to read or write to
these registers? So, does the peripheral will know about
this change?

Just to be clearer, as the term “I/O registers” is confused with “I/O
address space”, mapping “device registers” into system memory space allows
programs to modify the contents of those registers by simply modifying
memory addresses in system memory space. It is the processor host<->pci
chipset that performs the required PCI transaction when it observers a write
to one of these memory mapped system addresses.

I think that I understand about I/O address space. Someone
correct me if I’m not right, the architecture (i.e.
processor) can support I/O and memory space, and also the
system can be mapped only in the memory space. It depends
which architecture we are using. The processor sends the
address to the address line, some control signals are used to
select between I/O, memory (M/IO, Rd, Wr).

But, if the processor supports only memory space, I presume
that there is no M/IO signal. In addition, the peripherals
have I/O decoders and memory decoders. I don’t understand
how access to I/O registers if the processor supports only
the memory space.

If the processor does not support memory space, then on NT it must be the
case that the host<->pci chipset understands how to convert from a system
memory address to a PCI IO bus transaction, for ranges of system memory
addresses that are allocated specially for IO transactions. The device IO
registers are basically mapped into system memory, just as if they were
Memory registers, using these special memory addresses, and the platform
chipset takes care of ‘doing the right thing’.

I wrote an article (http://www.wd-3.com/archive/PioAccess.htm) for Windows
Driver Developer’s Digest (http://www.wd-3.com/) that covers some of the
details of device register access in NT. Perhaps you should read it.

5

I think that everything is working at the hardware level. But I’m
interested to know more about what your EE said :slight_smile:

Christian

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of David J. Craig
Sent: Wednesday, October 15, 2003 1:01 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] Re: IO vs memory mapping

Have a long talk with an EE. Devices are designed at the hardware level
for
port IO or memory mapped IO. Some CPUs don’t support one or the other,
but
the Intel i386 does support both.

“Christian Grenier” wrote in message
news:xxxxx@ntdev…
>
> I just want some explanation between I/O address and I/O-memory
mapping.
> I’m so confused about that.
>
>
> If the I/O registers are mapped in the main memory, the driver must
> access to this memory address to read or write to these registers?
So,
> does the peripheral will know about this change?
>
> I think that I understand about I/O address space. Someone correct me
if
> I’m not right, the architecture (i.e. processor) can support I/O and
> memory space, and also the system can be mapped only in the memory
> space. It depends which architecture we are using. The processor sends
> the address to the address line, some control signals are used to
select
> between I/O, memory (M/IO, Rd, Wr).
>
> But, if the processor supports only memory space, I presume that there
> is no M/IO signal. In addition, the peripherals have I/O decoders and
> memory decoders. I don’t understand how access to I/O registers if
the
> processor supports only the memory space.
>
> The MmMapIoSpace function is useful to map IO address space to memory
> space? I don’t understand how the memory address can access to the IO
> register.
>
> I hope to get some answers about this topic.
>
> Regards
>
> Christian
>
>
>
>
>

—
Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@mcdi.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

6

Thanks or your answers,

The Host/PCI chipset is the system master which knows if it has to
perform any tasks (IO transactions) after filtering the address. I
presume that the H/PCI chipset must know the address range to support.

I have the PCI System Architecture book from Mindshare and not a lot of
explanation about Host/PCI chipset. I think that it will be better for
me to learn more about this chipset. Maybe it has some books or
reference available.

Regards

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Roddy, Mark
Sent: Wednesday, October 15, 2003 1:47 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

That’s a lot of questions! I’ve added some comments in line below.

=====================
Mark Roddy

-----Original Message-----
From: Christian Grenier [mailto:xxxxx@mcdi.com]
Sent: Wednesday, October 15, 2003 12:56 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

I just want some explanation between I/O address and
I/O-memory mapping. I’m so confused about that.

If the I/O registers are mapped in the main memory, the
driver must access to this memory address to read or write to
these registers? So, does the peripheral will know about
this change?

Just to be clearer, as the term “I/O registers” is confused with “I/O
address space”, mapping “device registers” into system memory space
allows
programs to modify the contents of those registers by simply modifying
memory addresses in system memory space. It is the processor host<->pci
chipset that performs the required PCI transaction when it observers a
write
to one of these memory mapped system addresses.

I think that I understand about I/O address space. Someone
correct me if I’m not right, the architecture (i.e.
processor) can support I/O and memory space, and also the
system can be mapped only in the memory space. It depends
which architecture we are using. The processor sends the
address to the address line, some control signals are used to
select between I/O, memory (M/IO, Rd, Wr).

But, if the processor supports only memory space, I presume
that there is no M/IO signal. In addition, the peripherals
have I/O decoders and memory decoders. I don’t understand
how access to I/O registers if the processor supports only
the memory space.

If the processor does not support memory space, then on NT it must be
the
case that the host<->pci chipset understands how to convert from a
system
memory address to a PCI IO bus transaction, for ranges of system memory
addresses that are allocated specially for IO transactions. The device
IO
registers are basically mapped into system memory, just as if they were
Memory registers, using these special memory addresses, and the platform
chipset takes care of ‘doing the right thing’.

I wrote an article (http://www.wd-3.com/archive/PioAccess.htm) for
Windows
Driver Developer’s Digest (http://www.wd-3.com/) that covers some of the
details of device register access in NT. Perhaps you should read it.

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@mcdi.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

7

The host-pci chipsets are manufactured by people like intel via amd etc. and
it is their data sheets and programmer’s guides that provide insight into
how they operate. The Intel website is a pretty good place to browse for
interesting platform architecture documents :slight_smile:

The Mindshare PCI series are good, but they do not go into enough detail for
the host-pci chips that we are discussing to answer your questions.

=====================
Mark Roddy

-----Original Message-----
From: Christian Grenier [mailto:xxxxx@mcdi.com]
Sent: Wednesday, October 15, 2003 3:09 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

Thanks or your answers,

The Host/PCI chipset is the system master which knows if it
has to perform any tasks (IO transactions) after filtering
the address. I presume that the H/PCI chipset must know the
address range to support.

I have the PCI System Architecture book from Mindshare and
not a lot of explanation about Host/PCI chipset. I think
that it will be better for me to learn more about this
chipset. Maybe it has some books or reference available.

Regards

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Roddy, Mark
Sent: Wednesday, October 15, 2003 1:47 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

That’s a lot of questions! I’ve added some comments in line below.

=====================
Mark Roddy

> -----Original Message-----
> From: Christian Grenier [mailto:xxxxx@mcdi.com]
> Sent: Wednesday, October 15, 2003 12:56 PM
> To: Windows System Software Devs Interest List
> Subject: [ntdev] RE: IO vs memory mapping
>
>
> I just want some explanation between I/O address and
> I/O-memory mapping. I’m so confused about that.
>
>
> If the I/O registers are mapped in the main memory, the
> driver must access to this memory address to read or write to
> these registers? So, does the peripheral will know about
> this change?

Just to be clearer, as the term “I/O registers” is confused
with “I/O address space”, mapping “device registers” into
system memory space allows programs to modify the contents of
those registers by simply modifying memory addresses in
system memory space. It is the processor host<->pci chipset
that performs the required PCI transaction when it observers
a write to one of these memory mapped system addresses.

>
> I think that I understand about I/O address space. Someone
> correct me if I’m not right, the architecture (i.e.
> processor) can support I/O and memory space, and also the
> system can be mapped only in the memory space. It depends
> which architecture we are using. The processor sends the
> address to the address line, some control signals are used to
> select between I/O, memory (M/IO, Rd, Wr).
>
> But, if the processor supports only memory space, I presume
> that there is no M/IO signal. In addition, the peripherals
> have I/O decoders and memory decoders. I don’t understand
> how access to I/O registers if the processor supports only
> the memory space.
>

If the processor does not support memory space, then on NT it must be
the
case that the host<->pci chipset understands how to convert from a
system
memory address to a PCI IO bus transaction, for ranges of
system memory
addresses that are allocated specially for IO transactions. The device
IO
registers are basically mapped into system memory, just as if
they were
Memory registers, using these special memory addresses, and
the platform
chipset takes care of ‘doing the right thing’.

I wrote an article (http://www.wd-3.com/archive/PioAccess.htm) for
Windows
Driver Developer’s Digest (http://www.wd-3.com/) that covers
some of the
details of device register access in NT. Perhaps you should read it.

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@mcdi.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@stratus.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

8

> If the I/O registers are mapped in the main memory, the driver must

You cannot do this on x86.

Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
xxxxx@storagecraft.com
http://www.storagecraft.com

9

I lost the thread, cannot do precisely what ? Many graphics chips I worked
with exposed their 3Bx/3Cx/3Dx I/O space in a memory mapped range as well,
so that we could drive the sequencer and the CRT controller over a memory
interface and shave the I/O access overheads.

One other point that seems to be lost here is that memory and I/O spaces are
disjoint: the I/O space is only accessed by special instructions such as IN,
OUT, INS, OUTS, while other machine instructions access the memory space.
Although in theory it might be possible to DMA to and/or from I/O space, I
don’t know if any chip out there can do it. The PCI setup protocol
establishes where the memory and I/O addressing ranges lie, but it’s still
the processor’s responsibility to address the peripheral over memory or I/O
space. Another thing that might be possible is to get the bridge to do
conversion from memory to I/O access on the fly, but again, I’m not doing PC
development any longer so I don’t know if anyone does that. One thing to
keep in mind is, IA32 I/O instructions are not part of the RISC core and
hence they’re very slow compared to memory accesses. AFAIK they also don’t
use those beautiful write buffers and write combine circuitry, but here,
again, I may be wrong because I’m a tad rusty on this.

Alberto.

-----Original Message-----
From: Maxim S. Shatskih [mailto:xxxxx@storagecraft.com]
Sent: Thursday, October 16, 2003 9:23 AM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

If the I/O registers are mapped in the main memory, the driver must

You cannot do this on x86.

Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
xxxxx@storagecraft.com
http://www.storagecraft.com

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

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The contents of this e-mail are intended for the named addressee only. It
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and then destroy it.

10

> One other point that seems to be lost here is that memory and I/O spaces are

disjoint: the I/O space is only accessed by special instructions such as IN,
OUT, INS, OUTS, while other machine instructions access the memory space.

This was my point.

You cannot map the ports (IN/OUT) to memory space so that they will be
accessible as memory.

Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
xxxxx@storagecraft.com
http://www.storagecraft.com

11

  1. So, the only way to access the memory space is to use the MOV
    instruction. You can access to whole address memory space (0-4GB) -such
    as 32-bits address bus.

  2. If the processor doesn’t support IN and OUT instructions (PowerPC
    processor I think), the IO space is in fact into the memory space. So,
    you have to map the device IO space to virtual memory space (using
    MmMapIoSpace function). But, I know that x86 cpu supports the both (IO
    and memory space). Some PCI devices can have many BARs which support IO
    spaces. So, the driver should map this IO to memory space. But I don’t
    know how IO space (PCI device) can be accessed by the CPU if this one
    supports only the memory access. Is it the host-PCI bridge which
    prepares the IO transaction to the PCI device?

  3. What I know, the host-pci bridge contents the system memory space
    (PCI memory, AGP memory, BIOS, physical memory - SDRAM, swapping area?
    etc.) Specific regions are defined in this memory space. The host is
    responsible to execute the operations and send the requests to the good
    internal interface (memory controller, PCI, AGP, etc.).

Christian

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Maxim S. Shatskih
Sent: Thursday, October 16, 2003 2:27 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

One other point that seems to be lost here is that memory and I/O
spaces are
disjoint: the I/O space is only accessed by special instructions such
as IN,
OUT, INS, OUTS, while other machine instructions access the memory
space.

This was my point.

You cannot map the ports (IN/OUT) to memory space so that they will be
accessible as memory.

Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
xxxxx@storagecraft.com
http://www.storagecraft.com

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@mcdi.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

12

Do you know good reference book which explains system architecture (CPU

  • Host/PCI bridge, I/O and memory space, transactions between the CPU
    and the host)…

Regards
Christian
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Christian Grenier
Sent: Thursday, October 16, 2003 3:28 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

  1. So, the only way to access the memory space is to use the MOV
    instruction. You can access to whole address memory space (0-4GB) -such
    as 32-bits address bus.

  2. If the processor doesn’t support IN and OUT instructions (PowerPC
    processor I think), the IO space is in fact into the memory space. So,
    you have to map the device IO space to virtual memory space (using
    MmMapIoSpace function). But, I know that x86 cpu supports the both (IO
    and memory space). Some PCI devices can have many BARs which support IO
    spaces. So, the driver should map this IO to memory space. But I don’t
    know how IO space (PCI device) can be accessed by the CPU if this one
    supports only the memory access. Is it the host-PCI bridge which
    prepares the IO transaction to the PCI device?

  3. What I know, the host-pci bridge contents the system memory space
    (PCI memory, AGP memory, BIOS, physical memory - SDRAM, swapping area?
    etc.) Specific regions are defined in this memory space. The host is
    responsible to execute the operations and send the requests to the good
    internal interface (memory controller, PCI, AGP, etc.).

Christian

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Maxim S. Shatskih
Sent: Thursday, October 16, 2003 2:27 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

One other point that seems to be lost here is that memory and I/O
spaces are
disjoint: the I/O space is only accessed by special instructions such
as IN,
OUT, INS, OUTS, while other machine instructions access the memory
space.

This was my point.

You cannot map the ports (IN/OUT) to memory space so that they will be
accessible as memory.

Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
xxxxx@storagecraft.com
http://www.storagecraft.com

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@mcdi.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

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To unsubscribe send a blank email to xxxxx@lists.osr.com

13

  1. Any instruction that accesses memory writes to memory space. That
    includes moves, arithmetic/logic/etc. whose target is memory, and so on.

  2. I/O space is a concept that’s particular to Intel machines. If a chip has
    I/O addressable registers, the CPU must generate I/O decodes to that chip;
    this can be done by allocating a region of memory and telling the processor
    it should generate I/O decodes. I don’t have my PPC book handy but chances
    are that they will have some mechanism to use a range of memory to pretend
    it’s an I/O space.

  3. All that you mentioned is in the memory addressing space. There’s a 64Kb
    I/O space accessible through the IN/OUT instructions, that is, if your
    hardware supports or requires it.

Alberto.

-----Original Message-----
From: Christian Grenier [mailto:xxxxx@mcdi.com]
Sent: Thursday, October 16, 2003 3:28 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

  1. So, the only way to access the memory space is to use the MOV
    instruction. You can access to whole address memory space (0-4GB) -such
    as 32-bits address bus.

  2. If the processor doesn’t support IN and OUT instructions (PowerPC
    processor I think), the IO space is in fact into the memory space. So,
    you have to map the device IO space to virtual memory space (using
    MmMapIoSpace function). But, I know that x86 cpu supports the both (IO
    and memory space). Some PCI devices can have many BARs which support IO
    spaces. So, the driver should map this IO to memory space. But I don’t
    know how IO space (PCI device) can be accessed by the CPU if this one
    supports only the memory access. Is it the host-PCI bridge which
    prepares the IO transaction to the PCI device?

  3. What I know, the host-pci bridge contents the system memory space
    (PCI memory, AGP memory, BIOS, physical memory - SDRAM, swapping area?
    etc.) Specific regions are defined in this memory space. The host is
    responsible to execute the operations and send the requests to the good
    internal interface (memory controller, PCI, AGP, etc.).

Christian

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Maxim S. Shatskih
Sent: Thursday, October 16, 2003 2:27 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

One other point that seems to be lost here is that memory and I/O
spaces are
disjoint: the I/O space is only accessed by special instructions such
as IN,
OUT, INS, OUTS, while other machine instructions access the memory
space.

This was my point.

You cannot map the ports (IN/OUT) to memory space so that they will be
accessible as memory.

Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
xxxxx@storagecraft.com
http://www.storagecraft.com

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

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14

> > If the I/O registers are mapped in the main memory, the driver must

You cannot do this on x86.

But note that new PCI cards have both an IO space and a memory space that
expose the same registers, and you can use either one. So in a sense there
is sometimes memory mapped IO on a X86!

Loren

15

> MmMapIoSpace function). But, I know that x86 cpu supports the both (IO

and memory space). Some PCI devices can have many BARs which support IO

I don’t think that x86 ever allowed accessing the IO ports by MOV.

  1. What I know, the host-pci bridge contents the system memory space
    (PCI memory, AGP memory, BIOS, physical memory - SDRAM, swapping area?

There is no “PCI memory”, no “AGP memory” and no “swapping area” at this level.
There is just physical RAM.

Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation
xxxxx@storagecraft.com
http://www.storagecraft.com

16

> There is no “PCI memory”, no “AGP memory” and no “swapping area” at this
level.

There is just physical RAM.

I read it from Intel Chipset DataSheet. The chipset has defined a memory
space. Some regions are reserved for AGP, memory, BIOS, etc. So, the
chipset must decode the address from CPU and send it to the good interface
(memory,PCI,AGP,etc.).

17

> -----Original Message-----

From: Loren Wilton [mailto:xxxxx@earthlink.net]
Sent: Thursday, October 16, 2003 11:56 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

> > If the I/O registers are mapped in the main memory, the
driver must
>
> You cannot do this on x86.

But note that new PCI cards have both an IO space and a
memory space that expose the same registers, and you can use
either one. So in a sense there is sometimes memory mapped
IO on a X86!

Loren

There are x86 systems that have more than one PCI bus where on one bus the
IO space is exposed as IO to the processor and on the other bus the IO space
is mapped to memory. The translation is a function of the host-pci bridge
chip and not the processor.

=====================
Mark Roddy

18

As Mark Roddy pointed out, this is a function of either the board or the
bridge. There’s nothing that prevents a bridge from allowing the processor
to access a chip’s I/O space through a range of memory mapped addresses:
either the bridge or the peripheral will do the conversion.

The other thing is, in graphics there is such a thing as “AGP memory” which
isn’t necessarily physical RAM. The mapping between linear memory addresses
and real on-chip or on-board resources can be quite involuted !

Alberto.

-----Original Message-----
From: Loren Wilton [mailto:xxxxx@earthlink.net]
Sent: Thursday, October 16, 2003 11:56 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

> If the I/O registers are mapped in the main memory, the driver must

You cannot do this on x86.

But note that new PCI cards have both an IO space and a memory space that
expose the same registers, and you can use either one. So in a sense there
is sometimes memory mapped IO on a X86!

Loren

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@compuware.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

The contents of this e-mail are intended for the named addressee only. It
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it to anyone else. If you received it in error please notify us immediately
and then destroy it.

19

For some x86 architecture, the OS must know that I/O space is mapped to
memory space. The PCI device which I/O decoders are used to access to
I/O space, I presume that the bridge has the function to convert the
memory request to I/O request.

About CPU which supports I/O and memory access… The CPU can send I/O
(IN,OUT,…) or memory access (move instruction). The bridge knows the
memory and IO spaces. It converts the memory request (Read or Write)
into “read” or “write” transaction. PCI devices decode every transaction
(PCI specifications).

Christian

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Moreira, Alberto
Sent: Friday, October 17, 2003 10:07 AM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

As Mark Roddy pointed out, this is a function of either the board or the
bridge. There’s nothing that prevents a bridge from allowing the
processor
to access a chip’s I/O space through a range of memory mapped addresses:
either the bridge or the peripheral will do the conversion.

The other thing is, in graphics there is such a thing as “AGP memory”
which
isn’t necessarily physical RAM. The mapping between linear memory
addresses
and real on-chip or on-board resources can be quite involuted !

Alberto.

-----Original Message-----
From: Loren Wilton [mailto:xxxxx@earthlink.net]
Sent: Thursday, October 16, 2003 11:56 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] RE: IO vs memory mapping

> If the I/O registers are mapped in the main memory, the driver must

You cannot do this on x86.

But note that new PCI cards have both an IO space and a memory space
that
expose the same registers, and you can use either one. So in a sense
there
is sometimes memory mapped IO on a X86!

Loren

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@compuware.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

The contents of this e-mail are intended for the named addressee only.
It
contains information that may be confidential. Unless you are the named
addressee or an authorized designee, you may not copy or use it, or
disclose
it to anyone else. If you received it in error please notify us
immediately
and then destroy it.

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

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