Maybe Jake is in a better position to answer this ? But even if your hw
isn’t functional yet, it’s not that hard to put together a prototype on a
Xylinx gate array, maybe a day’s work of debugging Verilog HDL code ? The
software comes free with Ciletti’s HDL book, and wiring a prototype board is
also an easy job. You can take a look at www.xilinx.com or also at
www.xess.com for prototype boards.
Alberto.
-----Original Message-----
From: Taed Wynnell [mailto:xxxxx@vertical.com]
Sent: Monday, January 28, 2002 12:46 AM
To: NT Developers Interest List
Subject: [ntdev] How to register ISA interrupts that sit behind a PCI
bridge?
We have a somewhat odd setup where we have a few ISA cards that share a
single edge-triggered interrupt. These are not connected to the motherboard
directly, but actually sit behind a device which then converts it to PCI
(such as the PLX / Tundra products), and a single level-triggered interrupt.
Since the devices share an interrupt, they are obviously shared, but are
they edge- or level-triggered? From the motherboard’s point of view, it is
level-triggered. But since the actual devices are edge-triggered, maybe
that is how they should be registered?
This makes a difference due to the different algorithms used by NT to handle
shared interrupts. On shared level-triggered devices, the ISRs are called
until one of them returns TRUE. On shared edge-triggered devices, the ISRs
are called until ALL of them have returned FALSE.
Due to that, I think that registering them as edge-triggered would ensure
the correct behavior and avoid loss of interrupts. However, how will NT
react when we registered a PCI interrupt as edge-triggered?
(The hardware is not functional yet, so we can’t just try this out…)
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