I believe the memory controller takes care of ensuring consistency for
other things attempting to access it (like the PCI Controller)
-p
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Moreira, Alberto
Sent: Friday, November 14, 2003 8:44 AM
To: Windows System Software Devs Interest List
Subject: [ntdev] Re: Flushing DMA Buffer Allocated with AllocateC
ommonBuffer
I don’t see how it can work otherwise. For example, take a common-buffer
DMA where I’m writing a stream of commands to a graphics chip on the PCI
bus. If that buffer is writeback-cached, the processor is depositing the
data on its cache, and the cache lines are marked “modified” - however,
there’s no data actually written to physical memory, and it would take
another front-side bus master to access that memory to force the system
to dump the modified cache lines onto main memory. Now, the moment I
kick the DMA transfer alive, the DMA controller is going to go to memory
to fetch the stream of data, the only problem is, data isn’t there
because the buffer hasn’t been flushed from its cache lines. In fact,
some of that data may not even be in the cache yet, it may be lying in
the processor’s write buffers.
But processor caches stay coherent through the MESI protocol, which
operates at hardware level and is independent of the OS. That protocol
operates through every processor snooping every transaction on the
front-side bus.
But DMA controllers are masters on the PCI bus, not on the front-side
bus !
Hence, I see no way a DMA controller can be aware of the comings and
goings of the MESI protocol on the front-side bus.
For example, take a look at the DDK documentation for function
VideoPortStartDma(), it specifically says that the function flushes the
memory region in the host processor’s caches, then it builds a
scatter-gather list and calls HwVidExecuteDma().
Alberto.
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com]On Behalf Of Doug
Sent: Friday, November 14, 2003 11:05 AM
To: Windows System Software Devs Interest List
Subject: [ntdev] Re: Flushing DMA Buffer Allocated with
AllocateCommonBuffer
The documentation does require it. While the page in the DDK help
labeled “Using Common-Buffer Bus-Master DMA” makes no mention of
allocating an MDL and passing it to KeFlushIoBuffers, the page “Flushing
Cached Data during DMA Operations” infers it if you mark the buffers as
CacheEnabled.
Problem in the DDK docs?
“Mark Roddy” wrote in message news:xxxxx@ntdev…
> 3) common buffers are ‘special’. They are platform specific designed
> to be used for dma. The documentation in the DDK does not require that
> you flush common buffers.
>
> Note that on x86 platforms KeFlushIoBuffers is a NOP. Draw your own
> conclusions.
>
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