Re: Flushing DMA Buffer Allocated with AllocateC ommonBuffer

NTDEV
1

RE: [ntdev] Re: Flushing DMA Buffer Allocated with AllocateCommonBufferI
just allocated an MDL associated with the virtual address of the common
buffer and call KeFlushIoBuffers. I let the OS determine if it is a no-op or
not. On weird architectures (possibly like a Unisys ES7000), this may
actually be needed.

“Calvin Guan” wrote in message news:xxxxx@ntdev…
If you are writing NDIS drivers, you can use NdisMUpdateSharedMemory to
flush shared memory which is not described by any NDIS_BUFFER (MDL). Packet
descriptor structure accessed by both NIC and CPU falls into this category.
I couldn’t find the KeXxx counterpart of it. It’s defined as no-op for now
though.
Calvin Guan, Software Developer xxxxx@nospam.ati.com
SW2D-Radeon NT Core Drivers
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario, Canada L3T 7X6
Tel: (905) 882-2600 Ext. 8654
Find a driver: http://www.ati.com/support/driver.html

2

“Moreira, Alberto” wrote in message
news:xxxxx@ntdev…
>
> But processor caches stay coherent through the MESI protocol, which
operates
> at hardware level and is independent of the OS. That protocol operates
> through every processor snooping every transaction on the front-side bus.
> But DMA controllers are masters on the PCI bus, not on the front-side bus
!
> Hence, I see no way a DMA controller can be aware of the comings and
goings
> of the MESI protocol on the front-side bus.

In some high-end x86 chipsets, the I/O Hub controller participates
in the coherency protocol. The DMA controllers on the PCI buses do
not use a straight-through path to memory. I don’t know how many
chipsets have similar mechanisms.