RE: Accessing PCI Configuration Space from a software onl y driver

NTDEV
1

This whole thing could be handled so easily by the hardware, just apply a
lock when people write to CF8, so that the next request must be to CFC or
else orange smoke ensues. Or, meanwhile, queue anything else into a little
hw queue.

The Pentium already locks the bus when one writes to the SS, expecting a
write to ESP to follow. Why can’t PCI chips do something similar ?

Intel, are you listening ?

Alberto.

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com]On Behalf Of Vijay Anand
Sent: Monday, June 21, 2004 7:44 PM
To: Windows System Software Devs Interest List
Subject: Re: [ntdev] Accessing PCI Configuration Space from a software
only driver

Thanks Mark! Yes i know using CF8 / CFC is bad. Thats why i am trying to
rewrite portions of this
legacy driver to make it 64 bit / OS compliant…

I know HalGetBusData / HalSetBusData are obsolete and will not be supported
in future… Any idea
will these calls be supported in Windows XP-64 bit / Longhorn?

Thank you very much!

-Vijay

----- Original Message -----
From: “Mark Roddy”
To: “Windows System Software Devs Interest List”
Sent: Monday, June 21, 2004 4:19 PM
Subject: RE: [ntdev] Accessing PCI Configuration Space from a software only
driver

> Use the deprecated HalGetBusData routines in the DDK. Otherwise you have
to
> write a pci bus filter driver, and even then you will be way off into
> undocumented territory. By the way directly using cf8 is a bad idea,
> production driver or not, but I suspect you know that.
>
> > -----Original Message-----
> > From: xxxxx@lists.osr.com
> > [mailto:xxxxx@lists.osr.com] On Behalf Of Vijay Anand
> > Sent: Monday, June 21, 2004 7:08 PM
> > To: Windows System Software Devs Interest List
> > Subject: [ntdev] Accessing PCI Configuration Space from a
> > software only driver
> >
> > My new assignment is to maintain / port a validation (not a
> > production) driver that currently works on 2K / XP to 64 bit
> > compliant driver.
> >
> > This driver is not enumerated by PCI.sys but this driver
> > directly accesses PCI Configuration space using inline
> > assembly and CF8 / CFC registers.
> >
> > Since PCI.SYS is not enumerating this driver i cannot use
> > IRP_MN_READ_CONFIG and IRP_MN_QUERY_INTERFACE methods.
> >
> > So how to implement this pci config space access if my device
> > object stack doesnt include PCI.sys?
> >
> > Do i need to write a filter driver?
> >
> > Thanks,
> > Vijay
> >
> > —
> > Questions? First check the Kernel Driver FAQ at
> > http://www.osronline.com/article.cfm?id=256
> >
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>
>
>
>
> —
> Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256
>
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2

Well of course the first problem is that the PCI bus chips are not all from
Intel. The second problem is that just reading/writing one field of PCI
configuration space is rarely what people want, they want some significant
portion of the block, so your hardware solution doesn’t solve the problem
just moves it to a higher level.

New interfaces can make things nice for the OS developer, but it rarely the
case that you don’t have to support old hardware, protocols, or API’s that
make life painful.

–
Don Burn (MVP, Windows DDK)
Windows 2k/XP/2k3 Filesystem and Driver Consulting
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“Moreira, Alberto” wrote in message
news:xxxxx@ntdev…
> This whole thing could be handled so easily by the hardware, just apply a
> lock when people write to CF8, so that the next request must be to CFC or
> else orange smoke ensues. Or, meanwhile, queue anything else into a little
> hw queue.
>
> The Pentium already locks the bus when one writes to the SS, expecting a
> write to ESP to follow. Why can’t PCI chips do something similar ?
>
> Intel, are you listening ?
>
> Alberto.
>

3

I guess what I’m saying is, that kind of synchronization belongs in the
hardware. The software shouldn’t have to worry about that kind of thing.

Alberto.

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com]On Behalf Of Don Burn
Sent: Tuesday, June 22, 2004 9:25 AM
To: Windows System Software Devs Interest List
Subject: Re:[ntdev] Accessing PCI Configuration Space from a software
onl y driver

Well of course the first problem is that the PCI bus chips are not all from
Intel. The second problem is that just reading/writing one field of PCI
configuration space is rarely what people want, they want some significant
portion of the block, so your hardware solution doesn’t solve the problem
just moves it to a higher level.

New interfaces can make things nice for the OS developer, but it rarely the
case that you don’t have to support old hardware, protocols, or API’s that
make life painful.

–
Don Burn (MVP, Windows DDK)
Windows 2k/XP/2k3 Filesystem and Driver Consulting
Remove StopSpam from the email to reply

“Moreira, Alberto” wrote in message
news:xxxxx@ntdev…
> This whole thing could be handled so easily by the hardware, just apply a
> lock when people write to CF8, so that the next request must be to CFC or
> else orange smoke ensues. Or, meanwhile, queue anything else into a little
> hw queue.
>
> The Pentium already locks the bus when one writes to the SS, expecting a
> write to ESP to follow. Why can’t PCI chips do something similar ?
>
> Intel, are you listening ?
>
> Alberto.
>

—
Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: xxxxx@compuware.com
To unsubscribe send a blank email to xxxxx@lists.osr.com

The contents of this e-mail are intended for the named addressee only. It
contains information that may be confidential. Unless you are the named
addressee or an authorized designee, you may not copy or use it, or disclose
it to anyone else. If you received it in error please notify us immediately
and then destroy it.