I’ve read one of the archives discussing the implementation of DPCs, it says in certain conditions, when the OS believes the processor is not serving dpcs fast enough , when queuing a DPC a dispatch level interrupt will be issued , and once it is executed windows will loop trough the dpc queue and empty it but… isn’t that what the processor would do anyways ? how requesting a dispatch level interrupt speeds up things here?
it says in certain conditions, when the OS believes the processor is not serving dpcs fast enough
I don’t know what that means. There is some complex DPC queue latency stuff that CAN go on, but to the best of my knowledge the code path has been there since the earliest days of Windows NT almost never gets invoked. It’s arcane, complicated, and I’ve personally never spent the time to fully understand it.
when queuing a DPC a dispatch level interrupt will be issued
By default, each time a DPC is queued an IRQL DISPATCH_LEVEL software interrupt is generated.
The purpose of this is so that the DPC “interrupt handler” will run and service the list of pending DPCs. For one example, consider the need to process the DPC list as a result of servicing a timer expiration.
Does that help?
> @“Peter_Viscarola_(OSR)” said: > I don’t know what that means. There is some complex DPC queue latency stuff that CAN go on, but to the best of my knowledge the code path has been there since the earliest days of Windows NT almost never gets invoked. It’s arcane, complicated, and I’ve personally never spent the time to fully understand it. > > > By default, each time a DPC is queued an IRQL DISPATCH_LEVEL software interrupt is generated. > > The purpose of this is so that the DPC “interrupt handler” will run and service the list of pending DPCs. For one example, consider the need to process the DPC list as a result of servicing a timer expiration. > > Does that help? hmm , not sure, why do we need the handler to service the pending DPC list when the processor will do this himself when the IRQL drops from >= Dispatch Level to < Dispatch Level Or maybe it actually doesn’t ? And that’s why we have the dispatch level interrupt ?
maybe it actually doesn’t ? And that’s why we have the dispatch level interrupt
Correct on both counts.
Also, consider that the DPC being queued might not be queues to the DPC list on the current processor. In that case, how would the target processor become aware of the DPC without the interrupt being generated (in the cross-processor case, including the interprocessor interrupt).
1 Like