Mark & Yagmur,
I might have given the term PIO to Yagmur, implying not necessarily using
the specific i/o instructions of the x86 processor family. I was rather
referring to it on a looser term as “Programmed I/O”, which could be either
memory mapped or I/O mapped. Maybe we should call it “CPU-Driven access”,
CDA for short, instead, to not confuse the terms with something that means
something different to different people (where I come from, PIO registers
may well be mapped in the memory range, for instance on a 29K or 68K
processor, whilst it seems that the x86 world is more restricted to the I/O
instructions).
In either case, I would say that some form of DMA would definitely be the
preferred mode of operation, but if necessary, use memory mapped PIO.
As to the performance of CDA, it depends VERY much on what the interface
that the device is connected to. Here’s some reasonable assumptions:
- ISA-Bus/PCMCIA - Memory access - Runs at 8MHz or so. 16-bits wide. About
one transfer per 4 clock cycles: 2 * 8 / 4 = 4MB/s.
- ISA/PCMCIA - I/O instruction access. 8MHz, 16-bits wide. One transfer
per 8 clock cycles: 2 * 8/8 = 2MB/s.
- PCI. Runs at 33MHz. 32-bit wide. One transfer per 8 cycles. 4 * 33/8 =
16MB/s.
- PCI with burst access. 33MHz, 32-bit wide, one transfer per 1.5 cycles.
4 * 33/1.5 = ~85MB/s.
[I did these calculations in my head, using numbers from emmroy, so they
are approximations and the numbers of cycles are the best case number of
cycles per access, not the worst case].
These are best case scenarios, and assume that there is no delays caused by
other parts in the system, such as PCI bridge chips, other devices
accessing the buses needed to get there.
For instance the hard disc being accessed through the PCI bus will prevent
an ISA access getting through if the ISA bridge is connected via PCI. There
is currently no PC’s available which have a direct ISA access without going
through PCI bridge(s).
It may also be hard to convince the PCI bridge of doing burst cycles, so
don’t count on this unless you’ve proven to yourself that it can be done
(and if you have a generic platform, make sure it works on several
different hardware platforms, as the solution may be different for various
PCI bridges).
–
Mats
xxxxx@lists.osr.com wrote on 09/14/2004 06:27:20 AM:
PIO is exceptionally bad. And on certain processor links, it can get
even worse if the PIO is being bridged or translated on a bus.
I would strongly, at a bare minimum, look at changing the hardware
to do memory mapped I/O, but DMA is really what you need to do.
From: xxxxx@lists.osr.com on behalf of Yagmur Konuslu
Sent: Mon 9/13/2004 10:21 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] PIO Data Rate
Hi,
how much data can (or should be) transferred uinsg data?
While surfing on the net and reading some articels and books about this
topic, given examples are mouse clicks, keyboard strokes and the parallel
port. The case in this examples is either there is a small amount of data
or
speed is not important (for some degree). What’ s the case if the device
is
a network interface card? The scenario becomes even more dramatic if you
don’t have some buffer on the card. No DMA, no memory space.What can a
driver do for improving the performance of such a device (usage such a
device as a nic)?
Or stating shortly, should i change the hardware?
Best Regards
Yagmur Konuslu
Questions? First check the Kernel Driver FAQ at http://www.
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