We are designing a new gigabit Ethernet MAC ASIC.
I am software developer. The ASIC design requires
to write a control word (32-bit) “Per” transmit packet to
PIO (device memory).
I guess it is not good and would affect the Tx performance
dearly.
One register write per packet does not seem hugely expensive to me. Sounds
about usual. Each dma transaction generally requires some PIO-based setup
cost. Generally you want to worry more about how you can manage to perform
as many transactions per interrupt as possible, rather than worrying about a
small number of register read/write operations.
-----Original Message-----
From: kxverma [mailto:xxxxx@indiatimes.com]
Sent: Friday, March 29, 2002 8:27 AM
To: NT Developers Interest List
Subject: [ntdev] PIO access
Hi all,
We are designing a new gigabit Ethernet MAC ASIC.
I am software developer. The ASIC design requires
to write a control word (32-bit) “Per” transmit packet to
PIO (device memory).
I guess it is not good and would affect the Tx performance
dearly.
>We are designing a new gigabit Ethernet MAC ASIC.
I am software developer. The ASIC design requires
to write a control word (32-bit) “Per” transmit packet to
PIO (device memory).
I guess it is not good and would affect the Tx performance
dearly.
Let’s see, gigabit ethernet must do close to 2 million small packets/sec.
To xmit might require 2 million PCI bursts of 1 word (a burst is more than
1 PCI clock). It also seems possible you could group the writes and make
much larger bursts. This also does imply you have to write 8 MBytes/sec of
control words to sustain full wire speed. If your PCI target is happy to
gobble up and buffer writes, things may be ok. If your control word write
has a long ready latency, you will get a speed loss.
I think I’d have to defy my real answer to the famous “it depends”.
Analysis would take more than a 2 minute message. There is also receiving,
which we haven’t even mentioned.