Hello All,
Bit of a random question but it’s been bugging me and I was hoping to get your views on it.
There is this ancient HP article here: http://tinyurl.com/mnj6eoe that says the following -
“The PCI 2.2 specification (pages 202-204) dictates that root PCI bus must be allocated one block of MMIO addresses. This block of addresses is subdivided into the regions needed for each device on that PCI bus. And each of those device MMIO regions must be aligned on addresses that are multiples of the size of the region.”
Can you just confirm that the bit about the PCI 2.2 spec dictating the root PCI bus must be allocated 1 block of addresses is wrong.
I’ve checked the spec and it never mentions anything about 1 block and the spec doesn’t govern the host/root bridge bridge anyway.
So in theory, could a PCI root bridge say, for example, have 2 or more memory address windows e.g. 0xC0000000 - 0xCFFFFFFF and 0xD0000000 - 0xFFFFFFFF that is forwards onto the root PCI bus? This in theory could be done if the chip-set designers wanted, and then devices mapped into each seperate region? (not that this ever would be done, but in theory).
Any help would be appreciated,
Robert
xxxxx@live.com wrote:
Can you just confirm that the bit about the PCI 2.2 spec dictating the root PCI bus must be allocated 1 block of addresses is wrong.
I’ve checked the spec and it never mentions anything about 1 block and the spec doesn’t govern the host/root bridge bridge anyway.
So in theory, could a PCI root bridge say, for example, have 2 or more memory address windows e.g. 0xC0000000 - 0xCFFFFFFF and 0xD0000000 - 0xFFFFFFFF that is forwards onto the root PCI bus? This in theory could be done if the chip-set designers wanted, and then devices mapped into each seperate region? (not that this ever would be done, but in theory).
The PCI-to-PCI Bridge Specification certainly limits such a bridge to
one address range. There’s only one register in which to put the base
address and limit. And a PCIExpress root complex is such a bridge, so
I believe a PCIExpress root is limited to a single range.
However, the “PCI root bridge” is a different beast. It’s part of the
PCH chip. I’m not sure the behavior is specified anywhere. The few
resources I’ve found seem to indicate that the southbridge/PCH chips do
have only one slot in which to store the address range that gets routed
to PCI.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
Thanks for the reply Tim.
I’m not too sure, for example I know on the latest Haswell chips there are PCI memory ranges below and above 4GB, so I suppose that is technically 2 blocks of addresses being forwarded onto the PCI bus.
I think the reason most systems just have 1 block of contiguous address space is for ease and simplicity, but I don’t think the PCI 2.2 Spec dictates this?
Thanks again,
Robert
xxxxx@live.com wrote:
I’m not too sure, for example I know on the latest Haswell chips there are PCI memory ranges below and above 4GB, so I suppose that is technically 2 blocks of addresses being forwarded onto the PCI bus.
Haswell doesn’t do PCI at all. It’s entirely PCIExpress.
However, you seem to be correct. I’m looking at a web post with an
lspci listing for an Intel Xeon Phi co-processor that has one 128kB bar
and one 8GB bar. The Haswell put the smaller bar below 4GB and the
large one above (obviously). That’s a single device, so it can’t be
split between two different root complexes.
I think the reason most systems just have 1 block of contiguous address space is for ease and simplicity, but I don’t think the PCI 2.2 Spec dictates this?
No, that’s an implementation detail.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
Thanks,
I meant PCIe, it’s just Intel still say ‘PCI memory address’ region even on the newest CPU datasheets.
Can you send me the link to the lspci listing?
No, that’s an implementation detail.
Thanks, this is what i thought.
Kind Regards,
Robert
Hi Tim,
Just bumping this so you see it when you’re next online, Can you send me the link to the lspci listing?
Kind Regards,
Robert
On 29-Sep-2014 01:16, xxxxx@live.com wrote:
Hi Tim,
Just bumping this so you see it when you’re next online, Can you send me the link to the lspci listing?
Kind Regards,
Robert
But there simply can be more than one PCI segment (or “domain”),
each one has its window, then you have several disjoint windows.
IIRC this was discussed here not long ago.
– pa
On Sep 28, 2014, at 3:16 PM, xxxxx@live.com wrote:
Hi Tim,
Just bumping this so you see it when you’re next online, Can you send me the link to the lspci listing?
Yes, I saw it. I did that query at work, and I couldn?t reproduce it here. I?ll have to check it at the office.
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
Thanks Tim, much appreciated.
Tim Roberts wrote:
On Sep 28, 2014, at 3:16 PM, xxxxx@live.com wrote:
> Hi Tim,
>
> Just bumping this so you see it when you’re next online, Can you send me the link to the lspci listing?
Yes, I saw it. I did that query at work, and I couldn’t reproduce it here. I’ll have to check it at the office.
Man, there are few things as frustrating as knowing you saw a page and
not being able to find it again. Here’s the page:
http://www.pugetsystems.com/blog/2013/08/06/Will-your-motherboard-work-with-Intel-Xeon-Phi-490/
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
> Man, there are few things as frustrating as knowing you saw a page and
not being able to find it again. Here’s the page:
Haha yep.
Thanks for that Tim, appreciate it.
Hi Pavel A,
Sorry for not responding, only just seen your message.
“But there simply can be more than one PCI segment (or “domain”),
each one has its window, then you have several disjoint windows.
IIRC this was discussed here not long ago.”
As far as I know PCI segments can share the same memory and IO space so each segment could have a different ‘window’ of addresses, but if the 2 windows (the 128kb and the 8gb) are assigned to the same device, then those 2 windows must on the same segment.
I’m pretty certain at this point that root bridges can forward multiple bands of addresses onto the PCI bus behind it.
Thanks for your help with this everyone.
Kind Regards,
Robert
Hi again Pavel A
But there simply can be more than one PCI segment (or “domain”),
each one has its window, then you have several disjoint windows.
IIRC this was discussed here not long ago.
Just had another look, a PCI segment is only relating to the PCI config space. A PCI segment can contain 1 or more PCI root bridges and they all share the same memory and IO window.
Kind Regards,
Robert
On 30-Sep-2014 19:46, xxxxx@live.com wrote:
Hi Pavel A,
Sorry for not responding, only just seen your message.
“But there simply can be more than one PCI segment (or “domain”),
each one has its window, then you have several disjoint windows.
IIRC this was discussed here not long ago.”
As far as I know PCI segments can share the same memory and IO space so each segment could have a different ‘window’ of addresses, but if the 2 windows (the 128kb and the 8gb) are assigned to the same device, then those 2 windows must on the same segment.
I’m pretty certain at this point that root bridges can forward multiple bands of addresses onto the PCI bus behind it.
Thanks for your help with this everyone.
Kind Regards,
Robert
Yes, from the lspci that Tim R. referred to, it can be seen that there’s
only one domain there.
Regards,
– pa
On 01-Oct-2014 03:22, xxxxx@live.com wrote:
Hi again Pavel A
> But there simply can be more than one PCI segment (or “domain”),
> each one has its window, then you have several disjoint windows.
> IIRC this was discussed here not long ago.
Just had another look, a PCI segment is only relating to the PCI config space. A PCI segment can contain 1 or more PCI root bridges and they all share the same memory and IO window.
Kind Regards,
Robert
Hm, if so, maybe there are really two root bridges…
– pa
Hi,
Hm, if so, maybe there are really two root bridges…
The segment can be spread across 2 root bridges, with each root bridge having it’s own window of memory and I/O addresses, but if it’s 1 device (like the Xeon Phi) that has both the 128KB register and the 8GB assigned to it, then it must be behind the same root bridge as they are going to the same device.
I now know a root bridge can have 2 windows, if you look at the following datasheet for the Haswell system (which only has 1 root bridge), you will see on page 23 that it has 2 PCI memory range windows, 1 below 4GB and 1 above.
http://www.intel.co.uk/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-desktop-vol-2-datasheet.pdf
Kind Regards,
Robert