Newbie Question: SMI (what is it)?

NTDEV
1

I am going through an Intel doument (82371AB PCI-TO-ISA/IDE Xcelerator PIIX4)
and it mentioned that it has a way of sending an SMI (System Management
Interrupt)
which will cause the processor to go into System Management Mode.
Can somebody tell me what this mode is and if it is possible for me to write a
driver ISR
to handle this interrupt?
Thanks,

2

>I am going through an Intel doument (82371AB PCI-TO-ISA/IDE Xcelerator PIIX4)

and it mentioned that it has a way of sending an SMI (System Management
Interrupt)
which will cause the processor to go into System Management Mode.
Can somebody tell me what this mode is and if it is possible for me to write a
driver ISR
to handle this interrupt?

Hmmm, let’s see if I can explain SMM in less that a book. Intel processors
for a while now have a low-level execution mode that’s not real mode or 286
mode or 32-bit mode. I’d have to read the processor docs to be sure, but
believe SMM mode can ONLY be entered by asserting the SMI pin on the
processor. When this happens, the processor will start executing
instructions taken from a PHYSICAL address stored in an internal register
(which has a default value in the rom space as I remember). I believe SMM
mode is higher priority that NMI’s, and can’t be masked. SMM mode has lots
of very specific rules. Typically, the ROM BIOS will initialize the SMM
code address space. SMM mode is used for things like, scrubbing ECC memory
when a correctable fault occurs, or handling motherboard power suspend
mode. It can also be used to handle system failure debugging. There also
have been debugging tools that force the processor into SMM mode, and then
interact with processor through the external JTAG test pins (via a special
socket adapter).

I don’t believe it would be very easy to write a custom SMM mode handler
that you expected to run on any old computer. It would certainly not be a
normal “driver”, as memory addressing is not even compatible with a normal
driver. Another trick is the only way to change the physical address
register for SMM code is while running in SMM mode. If your shipping some
embedded computer, and you have control over the BIOS firmware, then SMM
mode might be useful. SMM mode is generally considered OS independent and
below any OS layer, although I could imagine an OS that worked with a
carefully designed SMM code to report things like correctable memory errors
and bus errors.

Read the processor manual if your curious. SMM mode is also processor model
specific. I’m not even sure non-Intel processors have SMM mode. It seems
like the Cyrix MediaGX processor used a SMM like mode to simulate normal
VGA registers on it’s video frame buffer.

  • Jan
3

Jan Bottorff wrote:

>I am going through an Intel doument (82371AB PCI-TO-ISA/IDE Xcelerator PIIX4)
>and it mentioned that it has a way of sending an SMI (System Management
>Interrupt)
>which will cause the processor to go into System Management Mode.
>Can somebody tell me what this mode is and if it is possible for me to write a
>driver ISR
>to handle this interrupt?

Hmmm, let’s see if I can explain SMM in less that a book. Intel processors
for a while now have a low-level execution mode that’s not real mode or 286
mode or 32-bit mode. I’d have to read the processor docs to be sure, but
believe SMM mode can ONLY be entered by asserting the SMI pin on the
processor. When this happens, the processor will start executing
instructions taken from a PHYSICAL address stored in an internal register
(which has a default value in the rom space as I remember). I believe SMM
mode is higher priority that NMI’s, and can’t be masked. SMM mode has lots
of very specific rules. Typically, the ROM BIOS will initialize the SMM
code address space. SMM mode is used for things like, scrubbing ECC memory
when a correctable fault occurs, or handling motherboard power suspend
mode. It can also be used to handle system failure debugging. There also
have been debugging tools that force the processor into SMM mode, and then
interact with processor through the external JTAG test pins (via a special
socket adapter).

I don’t believe it would be very easy to write a custom SMM mode handler
that you expected to run on any old computer. It would certainly not be a
normal “driver”, as memory addressing is not even compatible with a normal
driver. Another trick is the only way to change the physical address
register for SMM code is while running in SMM mode. If your shipping some
embedded computer, and you have control over the BIOS firmware, then SMM
mode might be useful. SMM mode is generally considered OS independent and
below any OS layer, although I could imagine an OS that worked with a
carefully designed SMM code to report things like correctable memory errors
and bus errors.

Read the processor manual if your curious. SMM mode is also processor model
specific. I’m not even sure non-Intel processors have SMM mode. It seems
like the Cyrix MediaGX processor used a SMM like mode to simulate normal
VGA registers on it’s video frame buffer.

  • Jan

Thanks a lot for the usefull info, I was thinking about using this is for an
embedded system,
but I think I know enough now to not pursue this particular option for now.

satrio

4

> Can somebody tell me what this mode is and if it is possible for me to
write a

driver ISR
to handle this interrupt?

I don’t think it is a good idea. This will disturb the pre-w2k hibernation &
power management features on some notebooks and brand names.
SMI is intended to switch to some very specific BIOS code regardless of
the status of the OS running on the machine. SMI is not intended for the OS
use - the OS has all other interrupts in its disposal.

Max