Maxim,
This was so only in the days of Pentium-166 and VX chipset, where the PCI INT# lines were
hard-wired to PIC inputs. ACPI BIOSes can reroute this mapping, especially if the
IO APIC is present which has 255 IRQs and not the good old PC/AT 16 ones.
First of all, single IO APIC normally has just 24 pins and not 255 as you say (although these days the same machine may have multiple IO APICs) -apparently, you just have confused IOAPIC with IDT.
Second, when it comes to APIC, the term “IRQ” is a bit misleading - it refers to IOAPIC pins, rather than PIC inputs. This is why you see such terms as “IRQ 22”, “IRQ 27” ,etc, although only 16 PIC inputs are available - the former means pin 22 of IOAPIC 1 , and the second one means pin 3 of IOAPIC 2.
Third, there is no need for ACPI to re-route IRQ to IOAPIC pins - non-ACPI MP BIOS can do it without a slightest problem (check MP Specifications for more info). Basically, there are 2 types of Interrupt Assignment Entries of MP Configuration Table, i.e. for PCI and ISA devices. In latter case, interrupt assignment entry just maps ISA IRQ to IOAPIC pin (normally sequentially, but at least one exception is always made).
In former case, interrupt assignment entry has the following format: “PCI bus A - device X - interrupts pin N - IOAPIC pin XXX”, where XXX holds both IOAPIC and pin number the way I have explained above. Therefore, in order to map PCI device to IRQ the system has to find an interrupt assignment entry in MP Configuration Table that matches bus, device, and InterruptPin-1 of the target device (InterruptPin field that is available from Configuration Space is always valid, although InterruptLine one is not when APIC is around - it applies only to PIC).
Every PCI devices has its own corresponding interrupt assignment entry in MP Configuration Table.Therefore, if the OS sees that the same IOAPIC pin number is specified in multiple interrupt assignment entries and devices in question are not MSI-capable, they have no option, other that sharing IRQ (i.e. IOAPIC interrupt pin), and once every IOAPIC pin may be mapped only to one interrupt vector, they have to share vector as well. If they are MSI-capable, then it can program them to raise interrupts via Message Address and Message data registers, rather than via pin, so that they can get assigned dedicated vectors…
Anton Bassov