We meet a problem of the USB 68013.
Just now ,we use the cypress providing WDF dirver and the CyAPI.lib, then we encounter a problem .
When there is no opertion( read/write ) on the usb bus for about 10 seconds , the 68013’ IFCLK will ?STOP? , this wil stop our FPGA because the FPGA is dirven by this clock . From the WIN7 ‘device manager’ driver property , we can find the Wdf driver’s power information changes from D0 to D2 .
We are not sure what’s wrong with it.
You have to ask cypress if they provide a way to disable runtime idle.
d
-----Original Message-----
From: xxxxx@lists.osr.com [mailto:xxxxx@lists.osr.com] On Behalf Of xxxxx@gmail.com
Sent: Tuesday, May 21, 2013 9:03 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] How to keep USB in D0 status.
We meet a problem of the USB 68013.
Just now ,we use the cypress providing WDF dirver and the CyAPI.lib, then we encounter a problem .
When there is no opertion( read/write ) on the usb bus for about 10 seconds , the 68013’ IFCLK will ?STOP? , this wil stop our FPGA because the FPGA is dirven by this clock . From the WIN7 ‘device manager’ driver property , we can find the Wdf driver’s power information changes from D0 to D2 .
We are not sure what’s wrong with it.
NTDEV is sponsored by OSR
OSR is HIRING!! See http://www.osr.com/careers
For our schedule of WDF, WDM, debugging and other seminars visit:
http://www.osr.com/seminars
To unsubscribe, visit the List Server section of OSR Online at http://www.osronline.com/page.cfm?name=ListServer
Hi,
If it is a test machine then you can disable the power optimization for the
time being using control panel.
On Wed, May 22, 2013 at 10:12 AM, Doron Holan wrote:
> You have to ask cypress if they provide a way to disable runtime idle.
>
> d
>
> -----Original Message-----
> From: xxxxx@lists.osr.com [mailto:
> xxxxx@lists.osr.com] On Behalf Of xxxxx@gmail.com
> Sent: Tuesday, May 21, 2013 9:03 PM
> To: Windows System Software Devs Interest List
> Subject: [ntdev] How to keep USB in D0 status.
>
>
> We meet a problem of the USB 68013.
>
> Just now ,we use the cypress providing WDF dirver and the CyAPI.lib,
> then we encounter a problem .
>
> When there is no opertion( read/write ) on the usb bus for about 10
> seconds , the 68013’ IFCLK will ?STOP? , this wil stop our FPGA because
> the FPGA is dirven by this clock . From the WIN7 ‘device manager’ driver
> property , we can find the Wdf driver’s power information changes from D0
> to D2 .
>
> We are not sure what’s wrong with it.
>
>
>
> —
> NTDEV is sponsored by OSR
>
> OSR is HIRING!! See http://www.osr.com/careers
>
> For our schedule of WDF, WDM, debugging and other seminars visit:
> http://www.osr.com/seminars
>
> To unsubscribe, visit the List Server section of OSR Online at
> http://www.osronline.com/page.cfm?name=ListServer
>
>
>
>
> —
> NTDEV is sponsored by OSR
>
> OSR is HIRING!! See http://www.osr.com/careers
>
> For our schedule of WDF, WDM, debugging and other seminars visit:
> http://www.osr.com/seminars
>
> To unsubscribe, visit the List Server section of OSR Online at
> http://www.osronline.com/page.cfm?name=ListServer
>
Disable power manager by device manager.
xxxxx@gmail.com wrote:
We meet a problem of the USB 68013.
Well, no, you have a problem in your design.
When there is no opertion( read/write ) on the usb bus for about 10 seconds , the 68013’ IFCLK will ?STOP? , this wil stop our FPGA because the FPGA is dirven by this clock . From the WIN7 ‘device manager’ driver property , we can find the Wdf driver’s power information changes from D0 to D2 .
We are not sure what’s wrong with it.
The problem is that your design is flawed. The purpose of IFCLK is to
let you synchronize your FPGA to feed bytes into the endpoint slave
FIFOs. It was not designed to act as a master clock for your FPGA.
Since there’s no point in allow you to fill the slave FIFOs when USB is
powered down, it’s natural that the clock stops.
If your FPGA still needs to operate even when USB is unavailable, then
you need to wire a separate clock to your FPGA. You can’t repurpose
IFCLK for this.
Otherwise, you need to design your FPGA to design clock stoppages like this.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
xxxxx@gmail.com wrote:
Just now ,we use the cypress providing WDF dirver and the CyAPI.lib, then we encounter a problem .
When there is no opertion( read/write ) on the usb bus for about 10 seconds , the 68013’ IFCLK will ?STOP? , this wil stop our FPGA because the FPGA is dirven by this clock . From the WIN7 ‘device manager’ driver property , we can find the Wdf driver’s power information changes from D0 to D2 .
The FX2 fires an interrupt when the host requests a SUSPEND. That
interrupt handler usually sets a flag that gets checked later in the
main polling loop. The polling loop then calls a routine that idles the
CPU. When the CPU is idled, that’s when the clocks stop. So, you
should be able to modify your firmware simply to ignore that bit.
However, that is not a friendly thing to do. It causes your device to
suck a lot more power than it should, and will drain laptop batteries.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.