Happy new year all!
Making the basic concept for a KMDF driver for an existing PCIe hardware, I
got stuck with 2 major questions:
- Sizes of SG Table, Transfers and Transactions:
The hardware takes a SG table with 16384 entries; each occupies 16 Bytes and
contains a 64 bit target address. Each SG elements address points to a fixed
chunk of 4096 bytes in the target buffer/MDL, i.e. it addresses full pages.
The control structure with the SG head index is maintained in another memory
location. The head index wraps automatically at the end of the SG table.
My plan is to create a WdfCommonBuffer of 256 MiB memory for the SG table
(accessed by the device contiguously) plus a smaller WdfCommonBuffer for the
head structure. The Read- or Writerequests from the application will always
use 16MiB buffers at even 4KB-page-addresses. This way I can set up DMA for
4 I/O requests at one time (16MiB is 4096 chunks of 4KB, SG table allows
4*4096 elements).
Do I get it right when implementing this like:
- WdfDeviceSetAlignmentRequirement(…, FILE_OCTA_ALIGNMENT)
- WDF_DMA_ENABLER_CONFIG_INIT(…, WdfDmaProfileScatterGather64,
16*1024*1024); i.e. transfer size is 16MiB (program the interrupt to fire
after 4096 SG elements) - Transaction size is the same as transfer size = 16MiB
- WdfDmaEnablerSetMaximumScatterGatherElements(…, 16*1024); i.e., the SG
table contains 16384 entries.
- Terms of “Read” or “Write”
The hardware does always both, reading the SG table and head table and
writing back there (updates head index, writes the actual length transferred
inside the 4KB chunk to each SG element). Is that random R/W in control
structures covered by the DMA abstraction?
Thanks very much, best regards,
Thoralf