Background:
- On Rev1 of our custom board, we have an NXP chip that collects a bunch of data from peripherals, and connects to the Windows host over USB.
- On Rev 2 of our custom board, I am working on the digital logic design (RTL) for a Lattice based FPGA, to enable PCIe Gen 3 for its P2P functionaility and other reasons the NXP chip is unable to handle, and it connects in the M.2 slot.
We want to send config from a Windows host and collect data continuously from the peripherals.
We will need to create a Windows device driver to handle these protocols.
Initially for Rev1, we want to read/write data to the NXP chip using USB (the firmware for the chip is built by other devs and functions).
For Rev2 we want to read/write data over M.2 PCIe to the FPGA.
(N.b. I have experience developing a Linux PCIe Gen4 driver for a Xilinx FPGA with success, mostly using skeleton code and enabling MSIX interrupts and sending data via DMA, and older Windows WDM experience).
Can you recommend me a plan on how to create this multi-protocol driver (WDM, KMDF? Sample codes? Architecture design, etc).
The reason it’s split up in this way is because Rev1 is showcased to stakeholders and has acceptance, thus I have to get data to and from this device. However, in a couple of months, a POC wants to be done on the FPGA I am designing as this will be the final target (or designed and taped-out as an ASIC if all goes well). Hence there is this multi-tiered approach.