Hi,
I am developing a driver for PCIe Gen3 capable EndPoint device for Win 7. The device does not support power management and does not advertise it in its capabilities.
When I do a disable of the device from Device Manager, the driver gets unloaded but the PCI bus driver is trying to set it to D3 state. This is resulting in configuration read failures and ultimately system hang. The problem scenario is same for both 64 bit and 32 bit OS.
Is there any way in which I can let the PCI bus driver know that my device does not support power management and it should not set it to D3 when I disable it? Is there any configurable parameter regarding the device power states?
Thanks in advance for any help or suggestion.
Is a PCIe device that doesn?t support power commands a conforming PCIe device? If not, you should fix your hardware.
You might try installed the checked pci.sys driver and turning on tracing. The pci driver knows how to spit out lots of useful comments on what it?s doing.
If you?re device is not actually PCIe conforming, and all other options are exhausted, you might see if the errata manager can help. Look for errata.inf. I?m not sure anybody outside Microsoft ever get?s to muck with the errata manager, although my memory is errata.inf can be edited.
Jan
On Aug 7, 2014, at 7:06 AM, xxxxx@hotmail.com wrote:
Hi,
I am developing a driver for PCIe Gen3 capable EndPoint device for Win 7. The device does not support power management and does not advertise it in its capabilities.
When I do a disable of the device from Device Manager, the driver gets unloaded but the PCI bus driver is trying to set it to D3 state. This is resulting in configuration read failures and ultimately system hang. The problem scenario is same for both 64 bit and 32 bit OS.
Is there any way in which I can let the PCI bus driver know that my device does not support power management and it should not set it to D3 when I disable it? Is there any configurable parameter regarding the device power states?
Thanks in advance for any help or suggestion.
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You mean your device doesn’t support D3, I take it. That’s not allowed. Your device is not PCIe compliant. From the most recent PCI spec I have:
“All Functions must support the D0 and D3 states” (section 5.3.1)
“D3 support is required.” (section 5.3.1.4)
Give up. Fix your device. That’s the only answer.
Peter
OSR
@OSRDrivers
xxxxx@hotmail.com wrote:
I am developing a driver for PCIe Gen3 capable EndPoint device for Win 7. The device does not support power management and does not advertise it in its capabilities.
When I do a disable of the device from Device Manager, the driver gets unloaded but the PCI bus driver is trying to set it to D3 state. This is resulting in configuration read failures and ultimately system hang. The problem scenario is same for both 64 bit and 32 bit OS.
I’m confused by your problem description. Is this a KMDF driver? Are
you calling WdfDeviceSetPowerCapabilities to advertise that you
stubbornly remain in D0 for every Sx state?
When you say “the PCI bus driver is trying to set it to D3 state”, are
you saying it’s trying to set your DRIVER into D3 state? It should only
do that if you told it you support D3, but even then, if you don’t have
a D3 state, you just return success.
How does this result in configuration read failures? Who is doing the
configuration read?
Is there any way in which I can let the PCI bus driver know that my device does not support power management and it should not set it to D3 when I disable it? Is there any configurable parameter regarding the device power states?
Have you not encountered WdfDeviceSetPowerCapabilities? That should
have come up in a Google search.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
Hi Tim,
The PCI block is in FPGA. FPGA’s do not support AUX power or bus power. According to SPEC D3 hot state is for devices which support bus power operation. Currently i am giving an external power supply to my board.
Also, we have set D0 and D1 support in endpoint PM capabilities of hardware. Accordingly I have set the power capabilities as below
WDF_DEVICE_POWER_CAPABILITIES_INIT(&powerCaps);
powerCaps.DeviceD1 = WdfTrue;
powerCaps.DeviceD2 = WdfFalse;
powerCaps.WakeFromD0 = WdfTrue;
powerCaps.WakeFromD1 = WdfTrue;
powerCaps.WakeFromD2 = WdfFalse;
powerCaps.WakeFromD3 = WdfFalse;
powerCaps.DeviceWake = PowerDeviceD1;
powerCaps.DeviceState[PowerSystemWorking] = PowerDeviceD0;
powerCaps.DeviceState[PowerSystemSleeping1] = PowerDeviceD1;
powerCaps.DeviceState[PowerSystemSleeping2] = PowerDeviceD1;
powerCaps.DeviceState[PowerSystemSleeping3] = PowerDeviceD1;
powerCaps.DeviceState[PowerSystemHibernate] = PowerDeviceD1;
powerCaps.DeviceState[PowerSystemShutdown] = PowerDeviceD1;
powerCaps.IdealDxStateForSx = PowerDeviceD1;
//Set Power Capabilities to Device
WdfDeviceSetPowerCapabilities(device,&powerCaps);
I am doing these settings in EvtDeviceAdd callback routine. The hang issue is seen after I return from my Add routine.
Even with this setting, Root Complex driver tries to put the device into D3 state, (if i try to disable the device from device manage) by writing into it’s config space. After writing to it’s config space the Root Complex driver is trying to read some other configurations from the end points config space, but all of them have timed out.
When i try to re enable the device the system is hanging.
Mr. Jonnalagadda… either you’re not hearing what I’m saying, or I completely misunderstand what you are saying.
Your device is not PCIe compliant. I quoted the spec sections that demonstrate this. Your device is not exempt from supporting D3 because your logic happens to be in an FPGA. In terms of this:
FPGA’s do not support AUX power or bus power
that makes no sense to me at all. If you don’t support bus power, how does your board get power? You have a separate cable from your board that runs to a power adapter that you plug into the wall?
What am I missing?
Peter
OSR
@OSRDrivers
xxxxx@osr.com wrote:
> FPGA’s do not support AUX power or bus power
that makes no sense to me at all. If you don’t support bus power, how does your board get power? You have a separate cable from your board that runs to a power adapter that you plug into the wall?
Yes, actually. He said exactly that.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.
He DID??
Hmmm… I see. He DID! Thanks Tim.
OK, so… my bad for not reading more closely.
However, does this make him exempt from implementing D3 according to the PCIe Spec? If he is, can you (once again) educate me and show me where in the spec it allows this?
PCIe spec aside, I seriously doubt that Windows will support this… I could be way wrong, but IIRC there’s an implicit assumption that all devices on PCI/PCIe will support D3(hot).
Peter
OSR
@OSRDrivers
xxxxx@hotmail.com wrote:
Even with this setting, Root Complex driver tries to put the device into D3 state, (if i try to disable the device from device manage) by writing into it’s config space. After writing to it’s config space the Root Complex driver is trying to read some other configurations from the end points config space, but all of them have timed out.
Why? If your device doesn’t go into D3, then your configuration space
should still be alive.
–
Tim Roberts, xxxxx@probo.com
Providenza & Boekelheide, Inc.