I just wanted to know how many minimum bus cycles wil be needed by a DMA.
Not sure what this has to do with Windows, but… ah… it can’t be less than 2, right?
Is that the answer you were looking for?
Peter
OSR
I’ll play the fool…
What’s a bus cycle? (Let’s see if you can define that in a world of
multiple memory controllers, packet-based I/O fabrics and processors with
multiple threads of execution.)
–
Jake Oshins
Hyper-V I/O Architect
Windows Kernel Group
This post implies no warranties and confers no rights.
wrote in message news:xxxxx@ntdev…
> Not sure what this has to do with Windows, but… ah… it can’t be less
> than 2, right?
>
> Is that the answer you were looking for?
>
> Peter
> OSR
>
>
A buscycle is like a clown car, only with more clowns, and better mileage.
Mark Roddy
On Thu, Nov 19, 2009 at 11:11 AM, Jake Oshins
wrote:
> I’ll play the fool…
>
> What’s a bus cycle? ?(Let’s see if you can define that in a world of
> multiple memory controllers, packet-based I/O fabrics and processors with
> multiple threads of execution.)
>
> –
> Jake Oshins
> Hyper-V I/O Architect
> Windows Kernel Group
>
> This post implies no warranties and confers no rights.
>
> --------------------------------------------------------------
>
>
> wrote in message news:xxxxx@ntdev…
>>
>> Not sure what this has to do with Windows, but… ah… it can’t be less
>> than 2, right?
>>
>> Is that the answer you were looking for?
>>
>> Peter
>> OSR
>>
>>
>
> —
> NTDEV is sponsored by OSR
>
> For our schedule of WDF, WDM, debugging and other seminars visit:
> http://www.osr.com/seminars
>
> To unsubscribe, visit the List Server section of OSR Online at
> http://www.osronline.com/page.cfm?name=ListServer
>
You guys are no fun… here I was, hoping to win a prize for being the first guy with the right answer, and you rain on my parade.
Peter
OSR
> What’s a bus cycle?
Actually, this is an interesting question - indeed, what is a “bus” on a system where every CPU has its own memory bank and memory controller is integrated directly into a processor die, Northbridge is not anywhere in sight , and chipset is a single chip that combines all of the features of a Southbridge with an AGP port and connects directly to the CPU???
Anton Bassov
wrote in message news:xxxxx@ntdev…
>> What’s a bus cycle?
>
> Actually, this is an interesting question
This is a bus cycle 
http://pavel_a.fastmail.fm/koshki/bus-cycle.jpg
–pa
Exactly! (only no clowns.)
Mark Roddy
On Fri, Nov 20, 2009 at 12:51 PM, Pavel A. wrote:
> wrote in message news:xxxxx@ntdev…
>>>
>>> What’s a bus cycle?
>>
>> Actually, this is an interesting question
>
> This is a bus cycle ?http://pavel_a.fastmail.fm/koshki/bus-cycle.jpg
>
> --pa
>
>
> —
> NTDEV is sponsored by OSR
>
> For our schedule of WDF, WDM, debugging and other seminars visit:
> http://www.osr.com/seminars
>
> To unsubscribe, visit the List Server section of OSR Online at
> http://www.osronline.com/page.cfm?name=ListServer
>