Disabling NT memory optimizations

NTDEV
1

I am having problems with HPI on a dsp board, and I believe the problems
may relate to nt caching memory, or optimizing my driver when I perform
the HPI read/writes. I am not using any pointer dereferencing, I am
religiously using the READ_REGISTER, and WRITE_REGISTER, but I can’t
seem to be rid of these problems. Are there ways to tell NT not to cache
or optimize my code in this regard?
The way that the hpi works, is that I write a control code to address A,
then an address location to address A+1, then I either read, or write,
depending on what I want to do, from address A+2, (or A+3 for more than
one dword). I am trying to figure out whether NT might not be fully
writing the control and address to A and A+1, before it attempts to do
the read from A+3?
Any ideas would be appreciated.

Nachum Kanovsky
Driver Development Team
xxxxx@mangodsp.com
02 5328706
011 972 2 532 8706

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2

Disabling NT memory optimizationsMmMapIoSpace has CacheEnable parameter.
As about sequencing (avoiding CPU’s out-of-order execution) - READ_REGISTER and WRITE_REGISTER guarantees it.

Max

----- Original Message -----
From: Nachum Kanovsky
To: NT Developers Interest List
Sent: Monday, December 31, 2001 12:43 PM
Subject: [ntdev] Disabling NT memory optimizations

I am having problems with HPI on a dsp board, and I believe the problems may relate to nt caching memory, or optimizing my driver when I perform the HPI read/writes. I am not using any pointer dereferencing, I am religiously using the READ_REGISTER, and WRITE_REGISTER, but I can’t seem to be rid of these problems. Are there ways to tell NT not to cache or optimize my code in this regard?

The way that the hpi works, is that I write a control code to address A, then an address location to address A+1, then I either read, or write, depending on what I want to do, from address A+2, (or A+3 for more than one dword). I am trying to figure out whether NT might not be fully writing the control and address to A and A+1, before it attempts to do the read from A+3?

Any ideas would be appreciated.

Nachum Kanovsky
Driver Development Team
xxxxx@mangodsp.com
02 5328706
011 972 2 532 8706

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3

Disabling NT memory optimizationsThere is no NT issue here, though perhaps there are hardware design problems.
Read/Write register use serializing instructions, and causes the IO space references to
be ordered on the memory bus. Others have seen problems with PCI bridge chips
in the past, but current high volume chipsets are probably OK at this point. I’d suspect
you’ve got some unique hardware.

What I’d normally do is add some delays in the software to show that this is
some kind of hardware race condition.

-DH
PS. This assumes you are running a vanilla HAL.
----- Original Message -----
From: Nachum Kanovsky
To: NT Developers Interest List
Sent: Monday, December 31, 2001 4:43 AM
Subject: [ntdev] Disabling NT memory optimizations

I am having problems with HPI on a dsp board, and I believe the problems may relate to nt caching memory, or optimizing my driver when I perform the HPI read/writes. I am not using any pointer dereferencing, I am religiously using the READ_REGISTER, and WRITE_REGISTER, but I can’t seem to be rid of these problems. Are there ways to tell NT not to cache or optimize my code in this regard?

The way that the hpi works, is that I write a control code to address A, then an address location to address A+1, then I either read, or write, depending on what I want to do, from address A+2, (or A+3 for more than one dword). I am trying to figure out whether NT might not be fully writing the control and address to A and A+1, before it attempts to do the read from A+3?

Any ideas would be appreciated.

Nachum Kanovsky
Driver Development Team
xxxxx@mangodsp.com
02 5328706
011 972 2 532 8706

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