Alberto, James, Max, et all…
thanx for providing all these information…
Has anyone tried using any disassemble/debuggger with the intel liturature
for the actual os fielder routines and hardware for sysenter and sysexit, XP
mainly relies on this, int 2e is may be for just backward compatiblity or
service
call extensibility. On XP, usually int2e route is absent, and I’ve seen it
by
providing a hook and burping msg ( nothing spits out)…
If there is any infos about the whole sequence of inst(s) and mechanics
available that
might be a good doc!!! It might be that by using MSR etc, the stack
copying/swaping between
usr/krnl is faster than the sys call dispatcher of nt/2k, but any
quantitative ananysis would be
great…, then may be punching in the NUMA/UMA, and hyperthreading etc ( may
be last one being
superficial)…
I’m saving these dialogues.
thanx
-prokash
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com]On Behalf Of Moreira, Alberto
Sent: Thursday, July 24, 2003 10:47 AM
To: Windows System Software Developers Interest List
Subject: [ntdev] Re: Context switching …
Note that the ring transition is a per-processor pure-hardware thing. P1
could be in Ring 0 while P2 is in Ring 3 or vice versa. The hardware level
transition is well documented in the Intel manuals. Also note that things
such as DISPATCH_LEVEL don’t exist in the hardware, they’re OS
abstractions; the hardware does what’s written in the IDT entry.
Alberto.
-----Original Message-----
From: James Antognini [mailto:xxxxx@mindspring.nospam.com]
Sent: Thursday, July 24, 2003 1:27 PM
To: Windows System Software Developers Interest List
Subject: [ntdev] Re: Context switching …
The transition from ring 3 to ring 0 has no effect on current process or
current thread. Amongst the things that do change:
- Full 4G (in 32-bit systems) addressability, versus only user-space
addressability.
- CPL 0 is in force.
- Kernel stack is used, once the interrupt handler instates it. That is,
this is purely the result of software.
- Libraries written for user-mode execution will not work. Again, this is a
software issue. A consequence is that it is usually not practicable to call
back into user space whilst remaining at CPL 0.
Things that do not change:
- Pageability, ie, ability to reference virtual storage that may not be
backed.
- Thread priority.
- Preemptiblity. I think this includes the time slice.
Off the top of my head, I cannot think of anything that would be different
on
a single- or multiple-CPU system. It’s true that on a single-CPU system,
going to DISPATCH_LEVEL will not involve physical disablement of interrupts,
but that’s not something related to the current question.
Michael Alekseev wrote:
is it TRUE that during switching
ring3 -> ring0 the thread’s context is not switched by OS even on
multi-CPU platform?
–
If replying by e-mail, please remove “nospam.” from the address.
James Antognini
Windows DDK MVP
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