I happen to be browsing the Pentium 4 docs and noticed it said the cache line
size was now 128-bytes, not the 32-bytes we all have know all these years.
Seems like the DDK function to return the cache line size on an x86 processor
was hard coded. A quick check of an older DDK version handy says “#define
KeGetDcacheFillSize() 1L”. I seem to remember noticing the bogus value once in
the past, and being forced to use a better value to program some hardware, like
32-bytes. Why isn’t this value pulled from the PCR, like
KeGetDcacheFillSize for
non-x86 processors?
This suggests DMA devices may act badly on systems with Pentium 4 processors.
PCI devices which tried really hard to do full cache line bursts will also now
often be doing partial cache line bursts, potentially having some performance
implications.
I’m assuming the Intel docs are not a misprint? Have to put it on my toask list
at next week’s Intel developers conference.
- Jan