I see on the PCI analyzer traces that a read operation occurs inside a burst of writes. The test I use does send data from RAM to the adapter’s prefetch space, however there are no reads in software. It could be that the read is triggered by the cpu cache protocol, however, not being an expert, I am looking for an explanation here. The easy answer could be that the adapter is broken; let me know the alternatives.
The read is always 4 bytes in size and does not occur at the same place. There are no read operations in the software.