@Josh1 you should never assume you will get every interrupt. By that I simply mean you should never be relying on the count of how many times your ISR gets called. If using legacy interrupts your hardware could generate multiple interrupt conditions while the interrupt is already asserted. Or I think back to back MSI interrupts could be combined by the OS and handled as one. However if you have a periodic interrupt you really should never miss one.
I dug out the PCIe Spec and it states:
If an implementation supports interrupts, then this specification requires support of either MSI or MSI-X or both. PCI Compatible INTx interrupt emulation is optional.
So I think it is a pretty safe assumption that you can always get one MSI vector. The only time I have seen a system not support MSI it was running VxWorks and they had explicitly turned it off.
If your hardware supports more than one vector you should handle getting fewer than your desired resources. Though the FPGA based designs I work with we have never handled it and it has never been a problem. Also depending on the design receiving for example 2 vectors instead of 4 can be really messy to handle.
I have seen two instances recently where legacy INTx interrupts were not supported. One was on a new server, unfortunately I do not know the model but this customer historically purchased HP servers. The other was an embedded system that the FPGA was downstream of the PCIe switch in a Nvidia Connect X7. The PCIe 7.0 spec still only says that INTx “may be deprecated in a future version”, but I have to wonder if we are going to start seeing fewer and fewer systems support it.