PCIe level TLP debugging is way beyond my abilities to diagnose, fix (or even comprehend …)
You say that, I bet, never having tried it.
Having lived for a few months with a PCIe bus analyzer, I can tell you… even as a humble software engineer… knowing exactly which registers are accessed when, and when each interrupt is generated by a device and how… is awesome.
Rant follows:
I’ve often said that one of the worst things to happen in hardware design is that with FPGAs everybody thinks they can build their own hardware. It lead to people who have no clue about computer architecture in general or Express in particular building devices. And this lack of knowledge invariably leads hardware that ranges from sad and sub-optimal to patently ridiculous. I guess one of the good things about this trend is that it allows us to offer more services to those who recognize the need. The problem is, most device builders think their IP will save them, and thus don’t see the need. Those PCIe DMA IPs take lots of parameters.
Not sayin this is you Mr. @craig_howard …. Totally not saying that at all. I’m thinking about my experiences over the many years. Soooo many truly smart client engineers who don’t know what they don’t know… but who want to argue over adding specific device features… and use, like, 32 MSIs when one will do.
Peter