> For the KMDF driver’s DMA part, DMA over USB and DMA over PCI should be similar
Surely not so. Looks like you don’t understand what is USB and PCI.
PCI is an onboard bus. The DMA-capable PCI device can really address the RAM directly (provided the arbitration phases are done OK) at device’s own will.
The memory controller (slave-only FSB-connected device) just can be a slave of both the CPU and the root PCI-to-FSB bridge. This usually requires only some trivial amount of software setup, usually done once by the BIOS at boot.
With PCIe, the things are the same, just the wiring between device<->PCI-to-FSB bridge (called “root complex” for PCIe) is serial and not parallel.
The new hardware (especially the one emulated for guests by hypervisors) also contains the device called IOMMU, which is an address translator between the DMAing PCI device and the memory controller, requiring some software setup on each transaction (not once at boot).
The IOMMU is managed by the OS transparently to the device driver - the driver just should use the OS’s DMA APIs properly.
Now about USB. First of all, USB is a polled bus. The device is always a slave, it cannot do any activities by its own.
Second, the USB transactions are more conceptually like TCP socket operations then like RAM addressing. There is no 1-to-1 mapping of USB to RAM.
Third, USB requires the rather complex host controller, which is a USB<->PCI bridge, and a complex device driver for it. Lots of software setup for each transaction.
Thus the very question of “USB DMA” is funny. USB host controller is yes, a PCI device, and does PCI DMA a lot, but all of this is hidden from the USB device and its driver. The USB protocol just has no notion of addressable memory, only about packets, pipes and transactions. USB is a protocol-based bus.
There is (was? is it still alive after death of MiniDV and with USB3-attached external hard drives?) also an interesting bus called 1394. It is a serial external protocol-based bus like USB, but… its protocol is much more complex and has the notion of addressable memory. Actually, any async 1394 transaction is a memory access to some addresses - read/write 32bit words, read/write blocks of memory and also interlocked operations on 32bit words.
This means that, with the most trivial software setup of the 1394 controller done once at boot, the 1394-connected device can really do DMA over the host’s RAM. In fact, the 1394 controller does this, but in this mode it just transparently maps the incoming 1394 transactions to PCI ones.
This mode is used by kernel debuggers (Windows for sure, and not only Windows I think), since it allows the debugger to read/write to the target memory without using any code running on a target CPU.
This also opens lots of security issues
(plug in a special 1394 device and save the snapshot of the host’s memory to it for later analyzis) but IIRC they were dealt with.
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Maxim S. Shatskih
Microsoft MVP on File System And Storage
xxxxx@storagecraft.com
http://www.storagecraft.com