Hi Eric,
Do you remember if it was streaming or memory mapped mode
I remember that we setup a set of S/G descriptors, and did a series of discrete transfers between host memory and FPGA memory (IOW, we didn’t continually stream data into host memory using XDMA… when we did this, we used the Address Translator).
I’m sorry I can’t be more helpful.
Peter
That does not sound strange to me. It sounds like a common interrupt moderation scheme. In fact many devices leave interrupts disabled while operating at their highest throughput by transitioning to a polling mode to improve overall system efficiency through a reduction in interrupts and context switches.
I assume that you are aware that in a design like this your DPC should be prepared to handle multiple events and must check the hardware for one more after re-enabling the interrupt. Both of these are to avoid data loss (or long delays)
Hi all,
Sorry for my late reply : bug hunting on friday afternoon and lost time reference ;-).
So,
@“Peter_Viscarola_(OSR)” thanks for your reply, It tells me that this is the Memory Mapped mode.
@MBond : you’re so right, I forgot this point for high speed card. Fortunately, this is not our case yet. At the moment, the minimal interrupt period is about 160us which can be correctly handled by current CPUs (3GHz and above). But we experience troubles even at low speed (4ms ISR period).
BTW, I’ll take your remark in note for our next release : a simple while() loop in the DPC will do the trick. THANKS !
Our last tests/fixes are leading us to another hypothesis : mix of DMA streams and registers accesses. Each are on separate BARs on the same card. If only DMA streams are actives : everything is fine. Troubles occur when we mixed DMA with registers accesses.
So it’s more an issue with the IP itself.
Did SO already heared this ?
To be continued …
Regards,
Eric.
Now, THAT is a plausible explanation. Verilog makes it pretty easy to confuse “this changes state immediately” and “this changes state at the next clock tick”, and the difference can trigger ugly errors.