A common DMA gotcha I’ve seen, especially on ARM platforms, is the need for a memory barrier between the write to the buffer and the write to trigger the DMA controller. This bit me BIG TIME on a PCIe driver in the past.
Most modern processors have “out of order” execution capabilities. Without the memory barrier, the write to memory can sometimes be incomplete by the time the DMA operation is triggered.
Greg
On Wed, 06 Oct 2021 17:46:10 +0000 (UTC), “Peter_Viscarola_(OSR)” wrote:
OSR https://community.osr.com/
Peter_Viscarola_(OSR) commented on PCIe dma not working as expected
Welcome to the community Mr. @DavidN – We’ll try to be gentle
Before we dive down into any more detail, can you confirm for me please that Common Buffer address that you’re giving to the hardware at the target for your DMA operations is the address you get from WdfCommonBufferGetAlignedLogicalAddress?
Are you using Simple DMA Mode or Scatter/Gather Mode for your transfers?
Also, please verify that you have WinDbg set up… and that you’re actually looking at the buffer in question via WinDbg. I assume that, setting up for a DMA write operation to memory (data coming FROM the device TO host memory), you initialize the buffer to something (just as a test, for example, you set it to all 0xFF or something), setup and do the DMA write to memory, then look at the memory buffer and see… that it hasn’t changed??
Peter