Actually, the processor won’t ask the PIC/APIC for the interrupt vector
until it issues a STI and accepts a new interrupt.
In the case of the PIC, there is no queuing, which turns out not to
matter with the protocols that the NT kernel uses (more on that in
another message.)
In the case of the Pentium 3 (and earlier APIC,) it queues up to two
interrupts per vector (or it might be per-priority level - I don’t
remember.) Again, this doesn’t matter given NT’s ISR protocol.
Jake Oshins
This posting is provided “AS IS” with no warranties, and confers no
rights.
-----Original Message-----
Subject: RE: Device Interrupt priority - Reviewing Jose Flores
From: “Christiaan Ghijselinck”
Date: Wed, 11 Dec 2002 10:57:32 +0100
X-Message-Number: 7
Correct, but it can hold only ONE ! See my previous answer on this theme
…
----- Original Message -----
From: “Maxim S. Shatskih”
To: “NT Developers Interest List”
Sent: Wednesday, December 11, 2002 10:20 AM
Subject: [ntdev] RE: Device Interrupt priority - Reviewing Jose Flores
> > issues an STI. This leaves a small window within which an interrupt
> could
> > theoretically be missed
>
> It will not. It will be put on hold on PIC/APIC.
>
> Max
>