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Modifying pcie switch config space for link training (80h capability register)

appuvivanappuvivan Member Posts: 4

I was looking for a windows exe User application to modify pci config space, especially capability offsets of 80h.
If you have any link for the windows sources that would run as exe, it would be great to help me out as i am new to windows.

Any Visual studio project doing this task to access switch config space would be a great help.


  • Tim_RobertsTim_Roberts Member - All Emails Posts: 14,837

    There are two problems here.

    First, PCI config space cannot be accessed from user space at all. It requires a kernel driver, and unless the kernel driver is a filter driver in the device's driver stack, whatever method it uses is unsupported and dangerous.

    Second, the capabilities register is not writeable. It is reporting status from the IP, not accepting commands.

    What on earth is the larger goal you're trying to accomplish?

    Tim Roberts, [email protected]
    Software Wizard Emeritus

  • appuvivanappuvivan Member Posts: 4

    Thanks Tim for the response, I am trying to do link training of the downstream devices on pcie bus. PCI link control register is writable wanted to access it at 80h of cfg space.
    So we cannot access switch config space in userspace at all? how to do link enable and disable ? in kernel mode only ? Any VS code reference if you have pls do share it.

  • Tim_RobertsTim_Roberts Member - All Emails Posts: 14,837

    I am trying to do link training of the downstream devices...

    No. You do not get to be involved in that. Link training happens at a hardware level at power-up time, LONG before any software of any kind has been loaded. The CPU is not involved in that task. And once negotiated, they are set for life. They cannot be changed without a reset.

    Link capabilities is register 0x8C. That's all read-only. Link control and status is in 0x90. A few fields are writable, but the negotiated link speed and width are not.

    What is the problem? Is your device training at the wrong rate?

    Tim Roberts, [email protected]
    Software Wizard Emeritus

  • appuvivanappuvivan Member Posts: 4
    edited November 2022

    I am trying to enable link and then disable link, to test the downstream devices for LT. Its the hw validation procedure which I wanted to put in the code to test Link Training.

    Link Control Register (Offset 10h)

  • Tim_RobertsTim_Roberts Member - All Emails Posts: 14,837
    edited November 2022

    Did you read the section where it says you should boot into a DOS-based environment to run that tool, before an operating system has loaded? There's a reason for that.

    You can ask Windows to disable and enable your PCIe switch in Device Manager, and that should cause a re-enumeration of its child devices. What you're doing might be easier in Linux. In Windows, those registers are all owned by the PCI/PCIe driver, and it is allowed to assume that no one else is dinking with them. Writing them from outside can easily trigger a blue screen.

    Usually, you test link training by resetting the system. Do you have a PCIe analyzer to capture the training?

    Tim Roberts, [email protected]
    Software Wizard Emeritus

  • appuvivanappuvivan Member Posts: 4

    Hi Tim, you were spot on with your information. Yes, it's easier in Linux than Windows for this. Need PCIe Analyzer tool for this ... Thanks for the response. Appreciate it!

  • Shane_CorbinShane_Corbin Member Posts: 309

    Another option that may or may not work for you is to boot to the EFI shell. You could even include python and chipsec. with UEFI Shell.html

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