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MSI-X / Interrupt Affinity

msrmsr Member Posts: 344
edited September 2019 in NTDEV


I have multiple MSI in old hw.
Vectors used by all interrupt events are driver configurable, so even if I get less MSI, I know the MsgID semantics. SW/FW did handshake etc.

I see my ISR is programmed in the IDT of all processors.
-Why is this required if ALL my MSI vectors are/can be targeted only to a specific processor.?
-Couldn't windows instead grant all my vectors, by finding a proc with enough free IDT entries instead of trying to find enough free entries in all procs?

I am trying to get MSI-X into my new device/fw and driver.

1) Spec - Function can have MSI or MSI-X or both, but only 1 enabled.
I guess in this case windows enables only MSI-X. Can HW just do away with MSI altogether and just do MSI-X?

2) Spec - Handling MSI-X Vector Shortages (--> Multiple MSI-X Table entries can have same vector)
But anyways windows grants either 1 or ALL MSI-X. In case only 1 MSI-X, how the MSI-X.Table (MsgCtrl.TableSize is > 1) configured
a) All MSI-X entries are (unmasked and) set to vector 0
b) Only MSI-X.TableEntry[0] is set to vector 0 and rest remain masked, and then FW doesn't/shouldn't generate/use those events/entries.

2.1) Also whose responsibility, driver or OS, to update the MSI-X table?
Seems mostly it is the OS task, but when is driver supposed to use this PCI_MSIX_TABLE_CONFIG_INTERFACE?

3) Seems IRP_MN_FILTER_RESOURCE_REQUIREMENTS is used to pin a particular MSI-X vector/interrupt to a particular core in KMDF driver (like it is done for NDIS/RSS).
In this case does the ISR for that vector is set only on that specific processor IDT (assume each of my interrupt/vector is using distinct Isr()?


Post edited by msr on
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