Others have answered your direct question, but to improve your performance with this data rate, you should consider applying interrupt moderation techniques. There is a wide range of academic research on this topic as well as several patented algorithms and the difference versus a trivial driver implementation can be dramatic.
The short version is that you should not plan for your ISR to handle just one ‘packet’. Not only is this not the contract with your chipset (interrupts can and are coalesced) but you will likely find that under some conditions disabling interrupts and polling provides better overall throughput
Sent from Surface Pro
From: Zvi Vered
Sent: Friday, August 14, 2015 3:05 AM
To: Windows System Software Devs Interest List
Hello,
My FPGA has 40 independent high speed (~7Gb/sec) input channels.
Each channel can cause a PCI express interrupt.
Upon an interrupt the WDF driver (in the ISR handler) has to read status register to see what channel caused the interrupt and then clear this register.
But after reading the status, there is a possibility that other channels will raise an interrupt.
After clearing the status, should I read the status again till it’s 0x0 or just wait to the next ISR ?
Is there a possibility that FGPA will create X PCI express interrupts messages but the ISR handler will be fired only X-y times ?
Best regards,
Z.V
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