Reading PCI Registers

Hi,

I want to read USB Base address from PCI registers. I tried following :

UsbBaseAddress = inw ( 0x20 ); ( this port is given in UHCI specification )

I am not getting proper value, i am getting 0xB800 under Win95 and in MS-Dos
i am getting 0x1010, i belive this is some junk value. Please give me some
pointer or sample ( C or ASM ) for this problem.

Thanks in advance,
Satish K.S


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> UsbBaseAddress = inw ( 0x20 ); ( this port is given in UHCI specification )

0x20 is PIC, and not PCI config space.

I am not getting proper value, i am getting 0xB800 under Win95 and in MS-Dos
i am getting 0x1010, i belive this is some junk value. Please give me some
pointer or sample ( C or ASM ) for this problem.

Any need in this register? Maybe usual PCI BAR0 will be OK?

Max


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Thanks Max,

Actually i want to read USB Base address which is present in PCI registers.
I got info to read PCI registers using “Int 0x1A” in DOS. It seems this PCI
structure is specific to Motherboard. How can we identify which motherboard
and which PCI structure we have to use ? Is there any generic way to do all
these things ?

Basically i want to Read USB Base address which is present in 0x20
( configuration offset ).

Thanks in advance,
Satish K.S

----- Original Message -----
From: “Maxim S. Shatskih”
To: “NT Developers Interest List”
Sent: Monday, January 28, 2002 9:23 AM
Subject: [ntdev] Re: Reading PCI Registers

> > UsbBaseAddress = inw ( 0x20 ); ( this port is given in UHCI
specification )
>
> 0x20 is PIC, and not PCI config space.
>
> > I am not getting proper value, i am getting 0xB800 under Win95 and in
MS-Dos
> > i am getting 0x1010, i belive this is some junk value. Please give me
some
> > pointer or sample ( C or ASM ) for this problem.
>
> Any need in this register? Maybe usual PCI BAR0 will be OK?
>
> Max
>
>
>
> —
> You are currently subscribed to ntdev as: xxxxx@aalayance.com
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> Actually i want to read USB Base address which is present in PCI registers.

I got info to read PCI registers using “Int 0x1A” in DOS. It seems this PCI
structure is specific to Motherboard.

Go directly to ports. There are 2 methods of accessing the PCI config space on x86, and IIRC all modern machines use only 1 of them.
These methods are not mobo-dependent.

Max


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If you go directly to the ports, then you’ll be bypassing the
OS-internal spinlock that guards them. This may cause (and, in many
cases, has caused) random data to be read or written from the PCI bus.
This can crash the machine and/or cause other random undefined behavior.

That’s why there are perfectly good mechansims for reading and writing
PCI config space built into the OS, which do take the spinlock before
any access. If you’re writing a WDM-compliant driver, then look into
using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
run on NT4, then use HalGet/SetBusData, or the miniport equivalent
versions of those.

If you just want to look at these things in the debugger, then use !pci.

The whole thread worries me a bit, though. There is a USB driver that
thinks it owns the ports that your grovelling around in. Again, you’ll
crash the machine if you try to use hardware that’s currently being
controlled by another driver.

  • Jake

-----Original Message-----

Subject: Re: Reading PCI Registers
From: “Maxim S. Shatskih”
Date: Mon, 28 Jan 2002 12:03:01 +0300
X-Message-Number: 9

> Actually i want to read USB Base address which is present in PCI
registers.
> I got info to read PCI registers using “Int 0x1A” in DOS. It seems
this PCI
> structure is specific to Motherboard.

Go directly to ports. There are 2 methods of accessing the PCI config
space on x86, and IIRC all modern machines use only 1 of them.
These methods are not mobo-dependent.

Max


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Anyway Thank u,

I am trying to reading PCI registers in Pure DOS in 16 bit mode ( This is
offtopic to this list, sorry for that ).

Thanks,
Satish K.S
----- Original Message -----
From: “Jake Oshins”
To: “NT Developers Interest List”
Sent: Tuesday, January 29, 2002 12:23 PM
Subject: [ntdev] RE: Reading PCI Registers

If you go directly to the ports, then you’ll be bypassing the
OS-internal spinlock that guards them. This may cause (and, in many
cases, has caused) random data to be read or written from the PCI bus.
This can crash the machine and/or cause other random undefined behavior.

That’s why there are perfectly good mechansims for reading and writing
PCI config space built into the OS, which do take the spinlock before
any access. If you’re writing a WDM-compliant driver, then look into
using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
run on NT4, then use HalGet/SetBusData, or the miniport equivalent
versions of those.

If you just want to look at these things in the debugger, then use !pci.

The whole thread worries me a bit, though. There is a USB driver that
thinks it owns the ports that your grovelling around in. Again, you’ll
crash the machine if you try to use hardware that’s currently being
controlled by another driver.

- Jake

-----Original Message-----

Subject: Re: Reading PCI Registers
From: “Maxim S. Shatskih”
Date: Mon, 28 Jan 2002 12:03:01 +0300
X-Message-Number: 9

> Actually i want to read USB Base address which is present in PCI
registers.
> I got info to read PCI registers using “Int 0x1A” in DOS. It seems
this PCI
> structure is specific to Motherboard.

Go directly to ports. There are 2 methods of accessing the PCI config
space on x86, and IIRC all modern machines use only 1 of them.
These methods are not mobo-dependent.

Max


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** Reply to message from “Satish K.S” on Tue, 29 Jan
2002 12:53:23 +0530

The INT 1AH interface that you’ve already found should work just fine for you
to read/write PCI config space. That’s the documented real mode DOS interface
to the PCI BIOS.

Sincerely,

Chris Myers
Senior Project Engineer
Quatech, Inc.

> Anyway Thank u,
>
> I am trying to reading PCI registers in Pure DOS in 16 bit mode ( This is
> offtopic to this list, sorry for that ).
>
> Thanks,
> Satish K.S
> ----- Original Message -----
> From: “Jake Oshins”
> To: “NT Developers Interest List”
> Sent: Tuesday, January 29, 2002 12:23 PM
> Subject: [ntdev] RE: Reading PCI Registers
>
>
> If you go directly to the ports, then you’ll be bypassing the
> OS-internal spinlock that guards them. This may cause (and, in many
> cases, has caused) random data to be read or written from the PCI bus.
> This can crash the machine and/or cause other random undefined behavior.
>
> That’s why there are perfectly good mechansims for reading and writing
> PCI config space built into the OS, which do take the spinlock before
> any access. If you’re writing a WDM-compliant driver, then look into
> using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
> run on NT4, then use HalGet/SetBusData, or the miniport equivalent
> versions of those.
>
> If you just want to look at these things in the debugger, then use !pci.
>
> The whole thread worries me a bit, though. There is a USB driver that
> thinks it owns the ports that your grovelling around in. Again, you’ll
> crash the machine if you try to use hardware that’s currently being
> controlled by another driver.
>
> - Jake
>
> -----Original Message-----
>
> Subject: Re: Reading PCI Registers
> From: “Maxim S. Shatskih”
> Date: Mon, 28 Jan 2002 12:03:01 +0300
> X-Message-Number: 9
>
> > Actually i want to read USB Base address which is present in PCI
> registers.
> > I got info to read PCI registers using “Int 0x1A” in DOS. It seems
> this PCI
> > structure is specific to Motherboard.
>
> Go directly to ports. There are 2 methods of accessing the PCI config
> space on x86, and IIRC all modern machines use only 1 of them.
> These methods are not mobo-dependent.
>
> Max
>
>
> —
> You are currently subscribed to ntdev as: xxxxx@aalayance.com
> To unsubscribe send a blank email to leave-ntdev-$subst(‘Recip.MemberIDChar’)@lists.osr.com
>
>
> —
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>If you go directly to the ports, then you’ll be bypassing the

OS-internal spinlock that guards them.

Surely, Jake, I know this.
But the question was on DOS USB driver implementation, not on WDM or NT driver.

Max


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The architecture has test and set instructions for that reason. If we’re
running at the lowest level and we need to talk to the hardware, sometimes
it’s easier, more expedient, and even safer, to talk directly to the
hardware and not rely on OS mechanisms.

And I thought a driver was supposed to own the hardware it drives ?

Alberto.

-----Original Message-----
From: Jake Oshins [mailto:xxxxx@windows.microsoft.com]
Sent: Tuesday, January 29, 2002 1:53 AM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

If you go directly to the ports, then you’ll be bypassing the
OS-internal spinlock that guards them. This may cause (and, in many
cases, has caused) random data to be read or written from the PCI bus.
This can crash the machine and/or cause other random undefined behavior.

That’s why there are perfectly good mechansims for reading and writing
PCI config space built into the OS, which do take the spinlock before
any access. If you’re writing a WDM-compliant driver, then look into
using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
run on NT4, then use HalGet/SetBusData, or the miniport equivalent
versions of those.

If you just want to look at these things in the debugger, then use !pci.

The whole thread worries me a bit, though. There is a USB driver that
thinks it owns the ports that your grovelling around in. Again, you’ll
crash the machine if you try to use hardware that’s currently being
controlled by another driver.

  • Jake

-----Original Message-----

Subject: Re: Reading PCI Registers
From: “Maxim S. Shatskih”
Date: Mon, 28 Jan 2002 12:03:01 +0300
X-Message-Number: 9

> Actually i want to read USB Base address which is present in PCI
registers.
> I got info to read PCI registers using “Int 0x1A” in DOS. It seems
this PCI
> structure is specific to Motherboard.

Go directly to ports. There are 2 methods of accessing the PCI config
space on x86, and IIRC all modern machines use only 1 of them.
These methods are not mobo-dependent.

Max


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> The architecture has test and set instructions for that reason. If we’re

running at the lowest level and we need to talk to the hardware, sometimes
it’s easier, more expedient, and even safer, to talk directly to the
hardware and not rely on OS mechanisms.

And I thought a driver was supposed to own the hardware it drives ?

Yes, but PCI config space is owned by HAL and not by the driver.

Max


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I thought the HAL was just an abstraction layer, just to bridge among
different architectures such as i386, Alpha and Mips. I didn’t know it owned
anything, and I’d rather see the PCI config registers owned by a PCI control
driver. In my mind, a piece of hardware is owned by its driver: the bus by
the bus driver, the device by the device driver, and so on. But I realize I
have a bit of an utopian view of the system, although I’m more ready than
other people to bypass it when it strikes my fancy !

Alberto.

-----Original Message-----
From: Maxim S. Shatskih [mailto:xxxxx@storagecraft.com]
Sent: Tuesday, January 29, 2002 12:44 PM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

The architecture has test and set instructions for that reason. If we’re
running at the lowest level and we need to talk to the hardware, sometimes
it’s easier, more expedient, and even safer, to talk directly to the
hardware and not rely on OS mechanisms.

And I thought a driver was supposed to own the hardware it drives ?

Yes, but PCI config space is owned by HAL and not by the driver.

Max


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And it becomes even more abstracted once the ACPI layer is introduced on
compliant machines.

Peter Scott
xxxxx@KernelDrivers.com
http://www.KernelDrivers.com

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Moreira, Alberto
Sent: Tuesday, January 29, 2002 11:26 AM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

I thought the HAL was just an abstraction layer, just to bridge among
different architectures such as i386, Alpha and Mips. I didn’t know it
owned
anything, and I’d rather see the PCI config registers owned by a PCI
control
driver. In my mind, a piece of hardware is owned by its driver: the bus
by
the bus driver, the device by the device driver, and so on. But I
realize I
have a bit of an utopian view of the system, although I’m more ready
than
other people to bypass it when it strikes my fancy !

Alberto.

-----Original Message-----
From: Maxim S. Shatskih [mailto:xxxxx@storagecraft.com]
Sent: Tuesday, January 29, 2002 12:44 PM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

The architecture has test and set instructions for that reason. If
we’re
running at the lowest level and we need to talk to the hardware,
sometimes
it’s easier, more expedient, and even safer, to talk directly to the
hardware and not rely on OS mechanisms.

And I thought a driver was supposed to own the hardware it drives ?

Yes, but PCI config space is owned by HAL and not by the driver.

Max


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As others have pointed out, I skimmed over the fact that the original
question was about how to read PCI config space from DOS. But this has
brought the conversation back around to NT.

A test-and-set instruction doesn’t help you when access to the entire
PCI config space is through an indexed-pair port mechanism. In order to
read or write data from a device, you write the bus number, device
number, function number, offset and an enable bit to port 0xcf8. Then
you read or write a DWORD to port 0xcfc.

The problem here is that the address you write to 0xcf8 may be replaced
by another address before you do your read or write to 0xcfc by another
thread, an ISR, a DPC or the SMI BIOS. If it is replaced by another
address, then you’ll end up either reading the wrong data or clobbering
somebody else’s stuff.

The OS has a spinlock, which it takes whenever you call the APIs. That
protects you against everything except the SMI BIOS. The SMI BIOS, if
it’s written correctly, shoots down all processors and then reads the
contents of 0xcf8, when it restores before it releases the processors.
This works, modulo a few thousand bugs.

Also, while a driver certainly owns the hardware it drives, in the WDM
world, the underlying PCI bus driver is the entity that owns almost all
of the common config header.

  • Jake

-----Original Message-----
Subject: RE: Reading PCI Registers
From: “Moreira, Alberto”
Date: Tue, 29 Jan 2002 10:10:38 -0500
X-Message-Number: 22

The architecture has test and set instructions for that reason. If we’re
running at the lowest level and we need to talk to the hardware,
sometimes
it’s easier, more expedient, and even safer, to talk directly to the
hardware and not rely on OS mechanisms.

And I thought a driver was supposed to own the hardware it drives ?

Alberto.

-----Original Message-----
From: Jake Oshins [mailto:xxxxx@windows.microsoft.com]
Sent: Tuesday, January 29, 2002 1:53 AM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

If you go directly to the ports, then you’ll be bypassing the
OS-internal spinlock that guards them. This may cause (and, in many
cases, has caused) random data to be read or written from the PCI bus.
This can crash the machine and/or cause other random undefined behavior.

That’s why there are perfectly good mechansims for reading and writing
PCI config space built into the OS, which do take the spinlock before
any access. If you’re writing a WDM-compliant driver, then look into
using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
run on NT4, then use HalGet/SetBusData, or the miniport equivalent
versions of those.

If you just want to look at these things in the debugger, then use !pci.

The whole thread worries me a bit, though. There is a USB driver that
thinks it owns the ports that your grovelling around in. Again, you’ll
crash the machine if you try to use hardware that’s currently being
controlled by another driver.

- Jake


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ahhh, It is dragging towards NT*.* :wink:

Basically i wanted to Read USB Base address from PCI Configuration
Structure, I read in the specification of UHCI, USB Base address will be
present in offset 0x20, can anybody give me details or sample to read in
16bit ( Real Mode ) either C or ASM.

Thanks a lot,
Satish K.S
----- Original Message -----
From: “Jake Oshins”
To: “NT Developers Interest List”
Sent: Wednesday, January 30, 2002 10:46 AM
Subject: [ntdev] RE: Reading PCI Registers

As others have pointed out, I skimmed over the fact that the original
question was about how to read PCI config space from DOS. But this has
brought the conversation back around to NT.

A test-and-set instruction doesn’t help you when access to the entire
PCI config space is through an indexed-pair port mechanism. In order to
read or write data from a device, you write the bus number, device
number, function number, offset and an enable bit to port 0xcf8. Then
you read or write a DWORD to port 0xcfc.

The problem here is that the address you write to 0xcf8 may be replaced
by another address before you do your read or write to 0xcfc by another
thread, an ISR, a DPC or the SMI BIOS. If it is replaced by another
address, then you’ll end up either reading the wrong data or clobbering
somebody else’s stuff.

The OS has a spinlock, which it takes whenever you call the APIs. That
protects you against everything except the SMI BIOS. The SMI BIOS, if
it’s written correctly, shoots down all processors and then reads the
contents of 0xcf8, when it restores before it releases the processors.
This works, modulo a few thousand bugs.

Also, while a driver certainly owns the hardware it drives, in the WDM
world, the underlying PCI bus driver is the entity that owns almost all
of the common config header.

- Jake

-----Original Message-----
Subject: RE: Reading PCI Registers
From: “Moreira, Alberto”
Date: Tue, 29 Jan 2002 10:10:38 -0500
X-Message-Number: 22

The architecture has test and set instructions for that reason. If we’re
running at the lowest level and we need to talk to the hardware,
sometimes
it’s easier, more expedient, and even safer, to talk directly to the
hardware and not rely on OS mechanisms.

And I thought a driver was supposed to own the hardware it drives ?

Alberto.

-----Original Message-----
From: Jake Oshins [mailto:xxxxx@windows.microsoft.com]
Sent: Tuesday, January 29, 2002 1:53 AM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

If you go directly to the ports, then you’ll be bypassing the
OS-internal spinlock that guards them. This may cause (and, in many
cases, has caused) random data to be read or written from the PCI bus.
This can crash the machine and/or cause other random undefined behavior.

That’s why there are perfectly good mechansims for reading and writing
PCI config space built into the OS, which do take the spinlock before
any access. If you’re writing a WDM-compliant driver, then look into
using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
run on NT4, then use HalGet/SetBusData, or the miniport equivalent
versions of those.

If you just want to look at these things in the debugger, then use !pci.

The whole thread worries me a bit, though. There is a USB driver that
thinks it owns the ports that your grovelling around in. Again, you’ll
crash the machine if you try to use hardware that’s currently being
controlled by another driver.

- Jake


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This cf8/cfc case is one where I wouldn’t hesitate demanding from hardware
manufacturers that violations of the state machine are thrown out on first
sight. If the chip is in the cfc state, throwing an i/o to its port cf8
should generate a handle-me-better-or-leave-me-alone interrupt. Or maybe
this is a case of actually using Peterson’s algorithm ?

Also, within the same processor, it’s a simple matter to use a
cli-cf8-cfc-sti sequence. Actually, that would have been one of the purposes
of the rep outs instruction, but alas, they allow interrupts within repeated
string instructions. They made an exception for the load ss/load esp
sequence, why can’t they make the same exception to two back-to-back in or
out instructions ? Imagine how uncool it would be to have to bracket an
lss/move-to-esp sequence with a call to an OS Spinlock API.

This would leave us only with the SMP issue to solve. Maybe someone should
get the PCI Sig to give us a mechanism that’s friendlier to multiprocessors
?

But I’m not sure whether the presence of a spinlock API is a deterrent to
ill behavior.

Alberto.

-----Original Message-----
From: Jake Oshins [mailto:xxxxx@windows.microsoft.com]
Sent: Wednesday, January 30, 2002 12:16 AM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

As others have pointed out, I skimmed over the fact that the original
question was about how to read PCI config space from DOS. But this has
brought the conversation back around to NT.

A test-and-set instruction doesn’t help you when access to the entire
PCI config space is through an indexed-pair port mechanism. In order to
read or write data from a device, you write the bus number, device
number, function number, offset and an enable bit to port 0xcf8. Then
you read or write a DWORD to port 0xcfc.

The problem here is that the address you write to 0xcf8 may be replaced
by another address before you do your read or write to 0xcfc by another
thread, an ISR, a DPC or the SMI BIOS. If it is replaced by another
address, then you’ll end up either reading the wrong data or clobbering
somebody else’s stuff.

The OS has a spinlock, which it takes whenever you call the APIs. That
protects you against everything except the SMI BIOS. The SMI BIOS, if
it’s written correctly, shoots down all processors and then reads the
contents of 0xcf8, when it restores before it releases the processors.
This works, modulo a few thousand bugs.

Also, while a driver certainly owns the hardware it drives, in the WDM
world, the underlying PCI bus driver is the entity that owns almost all
of the common config header.

  • Jake

-----Original Message-----
Subject: RE: Reading PCI Registers
From: “Moreira, Alberto”
Date: Tue, 29 Jan 2002 10:10:38 -0500
X-Message-Number: 22

The architecture has test and set instructions for that reason. If we’re
running at the lowest level and we need to talk to the hardware,
sometimes
it’s easier, more expedient, and even safer, to talk directly to the
hardware and not rely on OS mechanisms.

And I thought a driver was supposed to own the hardware it drives ?

Alberto.

-----Original Message-----
From: Jake Oshins [mailto:xxxxx@windows.microsoft.com]
Sent: Tuesday, January 29, 2002 1:53 AM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

If you go directly to the ports, then you’ll be bypassing the
OS-internal spinlock that guards them. This may cause (and, in many
cases, has caused) random data to be read or written from the PCI bus.
This can crash the machine and/or cause other random undefined behavior.

That’s why there are perfectly good mechansims for reading and writing
PCI config space built into the OS, which do take the spinlock before
any access. If you’re writing a WDM-compliant driver, then look into
using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
run on NT4, then use HalGet/SetBusData, or the miniport equivalent
versions of those.

If you just want to look at these things in the debugger, then use !pci.

The whole thread worries me a bit, though. There is a USB driver that
thinks it owns the ports that your grovelling around in. Again, you’ll
crash the machine if you try to use hardware that’s currently being
controlled by another driver.

- Jake


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> out instructions ? Imagine how uncool it would be to have to bracket an

lss/move-to-esp sequence with a call to an OS Spinlock API.

Context swaps (and lss is only for them) are protected by a spinlock anyway.

Max


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I can see the point of using a spinlock to protect the dispatch queues
themselves, that is, if one doesn’t already have a separate set of them
queues per processor anyway. But I’m not sure I see the need to protect the
context switch itself. And actually it is possible to context switch without
an lss/move-to-esp pair, you can either use the hardware architecture or,
even better, just push the old registers, flip CR3, and pop the new
registers.

And I can see myself wanting to use lss outside a context switch. :wink:

Alberto.

-----Original Message-----
From: Maxim S. Shatskih [mailto:xxxxx@storagecraft.com]
Sent: Wednesday, January 30, 2002 2:17 PM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

out instructions ? Imagine how uncool it would be to have to bracket an
lss/move-to-esp sequence with a call to an OS Spinlock API.

Context swaps (and lss is only for them) are protected by a spinlock anyway.

Max


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> I can see the point of using a spinlock to protect the dispatch queues

themselves, that is, if one doesn’t already have a separate set of them
queues per processor anyway.

Each CPU has a “ready thread” pointer, I suspect that all context swaps are done from current CPU’s thread to a “ready thread”.
Thus, a separate spinlock is possibly used to protect the “ready thread” pointer.

an lss/move-to-esp pair, you can either use the hardware architecture or,

Too slow. Linux used it once, then switched to software way.

even better, just push the old registers, flip CR3, and pop the new
registers.

Anyway you will need to switch ESP.

Max


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>That’s why there are perfectly good mechansims for reading and writing

PCI config space built into the OS, which do take the spinlock before
any access. If you’re writing a WDM-compliant driver, then look into
using BUS_INTERFACE_STANDARD. If you’re writing a driver that has to
run on NT4, then use HalGet/SetBusData, or the miniport equivalent
versions of those.

Except as I remember the HalGet/SetBusData will not let you program the
config regs of a PCI bridge under NT4. We had a big discussion about this
issue here a couple years ago. I personally was working on a PCMCIA device
that needed to work with cardbus adapters. The final conclusion was you
needed to get control of ALL the processors, raise the IRQL of the other
processors to a very high level, get the current processor/thread to
directly fiddle with the PCI config port pair, and then put everything
back. VERY ugly for frequent config space access, but ok for things like
driver initialization. This seemed like a case of MS code to “protect”
driver developers making things less stable. My bet would be MANY driver
developers who needed to access config registers on bridges did not do the
SMP synchronization.

  • Jan

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Heck, Alberto,

While you are at, why not write them in HTML? That way you can indent the
registers and tables! ;^)

-Evan

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com]On Behalf Of Moreira, Alberto
Sent: Tuesday, January 29, 2002 11:26 AM
To: NT Developers Interest List
Subject: [ntdev] RE: Reading PCI Registers

I thought the HAL was just an abstraction layer, just to bridge among
different architectures such as i386, Alpha and Mips. I didn’t
know it owned
anything, and I’d rather see the PCI config registers owned by a
PCI control
driver. In my mind, a piece of hardware is owned by its driver: the bus by
the bus driver, the device by the device driver, and so on. But I
realize I
have a bit of an utopian view of the system, although I’m more ready than
other people to bypass it when it strikes my fancy !

Alberto.


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