> everywhere, but can somebody explain exactly how the cache coherency
protocol gets violated in this case and memory access gets
potentially
incoherent?
Imagine the same page double-mapped to the address space by 2
different PTEs, one with caching on, other with caching off.
Now imagine some code writes a value via noncached PTE. The value is
updated in memory and not updated in the cache. The read from cached
PTE will read the stale value.
This is a good old problem which is known to people working on
hardware which requires the software to know on cache coherency issues
(i.e. PowerPC).
Max