Re: [ntdev] Windows kernel code page alignment

NTDEV
1

What led you to expect that instructions wouldn’t cross page boundaries? And further, what led you to expect that this would be a performance issue? What specifically would you expect to be slower / a problem?

As for your actual question, just ensure that all of the pages occupied by executable code have the execute bit set. If you are trying to do this dynamically, you’ll have to be more specific if you want help

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Why should it? I don’t get your concern. You don’t like that some instructions
cross page boundaries?
Wouldn’t there be a performance implication otherwise? Of course, the gravity of it would be predicated on the hit count of the instruction in question. My concern although is not performance in the case I am looking at but stems from how I guard the page, slightly off topic.

I think this is the responsibility of the linker. I would expect the kernel
loader to respect all alignment requirements via ambivalence since it will load
sections from the image on page boundaries. Or something like that.
Right, I don’t expect the loader to fixup rather the linker to do the necessary adjustments. Or at least, I assumed linkers do that by default but they don’t appear to…

I don’t even understand the question.

This -

82a66ffb 0f848f010000 je nt!MmUnsecureVirtualMemory+0xe29 (82a67190)
82a67001 8b5d08 mov ebx,dword ptr [ebp+8]

If you look at the instruction at 82a66ffb, it crosses page boundary on the system/version in question, something I wasn’t expecting.

Kamala

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2

Your presumption is that it will be paged in for only a single instruction. That would be a worst case scenario. Except for perhaps the last page in an executable region, one would expect each page to contain thousands of instructions and except under memory pressure it won’t be paged out. Thrashing is a well known problem on all VM or multi-tasking OSes and is no worse here than anywhere else

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That would just be a gigantic waste of critical resources.

What would happens if the code belongs to a paged section and the particular page that was allocated for one instruction happens to be paged out ? The result would be hundred or thousand of instructions being executed to satisfy just one instruction. That is not optimization.

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3

Think carefully. What is the alternative to having an instruction span a page boundary? Assuming that you can’t make the code smaller, the only other choice is to pad the last bytes of page A so that the instruction begins in page B. Even if this instruction is the only one needed on that page, the page will still have to be brought in.

Enforcing alignment can only increase code size and increasing code size can’t reduce the need for page faults except for the case of jumping backwards (ie to the start of loop)

The question is whether an instruction that crosses a page boundary somehow will affect the performance of the CPU pipeline. Obviously, this will depend on the exact hardware, but when compiling code that will run on a variety of hardware, making the code bigger to possibly improve the execution of a single instruction seems like a poor choice

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But remember that alignment has a global effect. The loader cannot ensure a
larger-grained alignment than the loader, which cannot ensure a larger-grained
alignment than the compiler. So if the compiler is only compiling for 32-byte
alignment, the linker and loader cannot enforce page alignment.

I won’t dispute the loader/linker/compiler role and effect here.

Thinking through this again, I am suspecting, data if we collect any would belie our current general assumption that this is a non-issue nowadays (which while true in most cases) though in reality, in some scenarios this is going to be an issue gone unnoticed because of the general assumption around it.

That said, this thread did help sanity check my assumption although the issue stemming from it need fixing which is off topic and for me to take care of. Thanks for all your input!

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