Questions on TLB

Hello,
I want the answers to these following questions.

  1. Is TLB and level 1 & 2 caches are same?
  2. What is TLB thrashing?
  3. How many entries will be in TLB for code & data?
  4. In 32 bit windows OS , we can deploy 4GB of physical memory. This
    upper limit is including/excluding caches?

Can some one explain this in slightly greater detail. If you can refer
me to some document as well related to this, it would help:

Thanks
-Raja

http: — Questions?
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I could explain this to you, but it would be redundant , since TLB , and memory architecture of IA32 and related CPUs is debated on Intel Pentium q,2,3,4, CPU datasheets and software developer mnulas, at a much greater detail then it can be done in this list. Dowload them freely at Intel’s developer site.

Also, this list is about Windows NT system level programming, and not about processors / chipset details.

Dan

----- Original Message -----
From: Kannan, Raja
To: Windows System Software Devs Interest List
Sent: Monday, August 08, 2005 1:47 PM
Subject: [ntdev] Questions on TLB

Hello,
I want the answers to these following questions.

  1. Is TLB and level 1 & 2 caches are same?
  2. What is TLB thrashing?
  3. How many entries will be in TLB for code & data?
  4. In 32 bit windows OS , we can deploy 4GB of physical memory. This upper limit is including/excluding caches?

Can some one explain this in slightly greater detail. If you can refer me to some document as well related to this, it would help:

Thanks
-Raja

— Questions? First check the Kernel Driver FAQ at http://www.osronline.com/article.cfm?id=256 You are currently subscribed to ntdev as: unknown lmsubst tag argument: ‘’ To unsubscribe send a blank email to xxxxx@lists.osr.com

Questions? First check the Kernel Driver FAQ at http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: unknown lmsubst tag argument: ‘’
To unsubscribe send a blank email to xxxxx@lists.osr.com

Thanks Dan. I am looking in to the “System Programming guide” for IA32.

Raja


From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Dan Partelly
Sent: Monday, August 08, 2005 4:28 PM
To: Windows System Software Devs Interest List
Subject: Re: [ntdev] Questions on TLB

I could explain this to you, but it would be redundant , since TLB , and
memory architecture of IA32 and related CPUs is debated on Intel Pentium
q,2,3,4, CPU datasheets and software developer mnulas, at a much greater
detail then it can be done in this list. Dowload them freely at Intel’s
developer site.

Also, this list is about Windows NT system level programming, and not
about processors / chipset details.

Dan

----- Original Message -----
From: Kannan, Raja mailto:xxxxx
To: Windows System Software Devs Interest List
mailto:xxxxx
Sent: Monday, August 08, 2005 1:47 PM
Subject: [ntdev] Questions on TLB

Hello,
I want the answers to these following questions.

1) Is TLB and level 1 & 2 caches are same?
2) What is TLB thrashing?
3) How many entries will be in TLB for code & data?
4) In 32 bit windows OS , we can deploy 4GB of physical memory.
This upper limit is including/excluding caches?

Can some one explain this in slightly greater detail. If you can
refer me to some document as well related to this, it would help:

Thanks
-Raja

http:
Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256 You are currently subscribed
to ntdev as: unknown lmsubst tag argument: ‘’ To unsubscribe send a
blank email to %%email.unsub%%

Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: unknown lmsubst tag
argument: ‘’
To unsubscribe send a blank email to %%email.unsub%%


Questions? First check the Kernel Driver FAQ at
http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: unknown lmsubst tag argument:
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Thanks Andy,
I have some doubt in this line.

From DDK: “The MmAllocateNonCachedMemory routine allocates a virtual
address range of noncached and cache-aligned memory.”

So the allocated address space will be in RAM and not in cache. Than
what “cache-aligned memory” means?

Raja

-----Original Message-----
From: Andreas Haeber [mailto:xxxxx@online.no]
Sent: Monday, August 08, 2005 5:04 PM
To: Kannan, Raja; Windows System Software Devs Interest List
Subject: SV: [ntdev] Questions on TLB

Hi Kannan,

In a normal computer architecture (like a desktop PC) you have a memory
hierarchy. The destination of the memory is to feed the CPU (or DMA
controllers, but let’s drop that here). Ultimately the CPU uses
registers to read and write data. Registers are the quickest memory
storage for the CPU.

At the other side you’ve got much slower memory storage: RAM, hard
disk drives, tape drives, and similar. But these have other properties
which make them very useful, like being cheap and persistent.

Since RAM is so slow, compared to CPU registers, caches are introduced
between them. First you only had one cache at the CPU, but now several
levels are introduced: L1, L2, etc. Notice that this has nothing to do
with TLB. But for some data stored in TLB it must be moved from
wherever-it’s-stored down to the CPU registers to be used by the CPU.

  1. Is TLB and level 1 & 2 caches are same?
    No. TLB is needed with virtual memory. You can have L1… Lx caches
    without any TLB at all, using “unvirtual” memory.
  1. What is TLB thrashing?
    A cache is most useful if the content stored there is used again, and
    not changed too often. Thrashing means that the cache/buffer content is
    changed too often.
  1. How many entries will be in TLB for code & data?
    Depends on the TLB…
  1. In 32 bit windows OS , we can deploy 4GB of physical memory. This
    upper limit is including/excluding caches?

Excluding caches. The limit comes from the amount of memory/data the
system can address. When accessed/needed this memory will be copied down
to the caches, and if the CPU altered it (i.e. a write operation) it is
moved up to the RAM and stored there. But there is latency involved in
this…

Can some one explain this in slightly greater detail. If you can refer

me to some document as well related to this, it would help:

You can read a lot more about this in “Computer Architecture: A
quantitative approach” by Hennessy and Patterson. You should easily find
it at Amazon and other bookstores with computer litterature. Also you
should be able to find whitepapers etc. from AMD, Intel and other CPU
producers. But a good book about computer architecture should be helpful
to read before going to the CPU makers manuals.

I’m sorry for any errors I’ve written here, and hope that anybody will
correct me where I’m wrong. Especially the TLB trashing explanation is
not very good :slight_smile:

–andy

  1. No. TLB are associative virtual to page descriptor translator used to speed up page translation while L1 and L2 caches are purely ‘physical’ . In other words, TLB is a fast way to give the processor the physical address corresponding to a virtual address without the need to incurr in expensive page address translation.
  2. Thrashing means TLB entries going out of the cache. The worst scenary is all entries going out at the same time which happens for example when switching contexts. A system that switches contexts often thrases the TLB often. For example, NT/W2K is a perfect example of ‘too much thrashing’ TLBs on SMP systems.
  3. In most processors there are between 32 to 128 entries. Note that TLB size is measured in ‘entries’ not in KBs. TLB code and data caches are separated and usually they have different sizes. There are control registers in the CPU to read exactly TLB configuration for each processor (see CPUID instruction).
    The size of the TLB is optimized according to CPU performance. Usually higher CPU speeds means lower TLB sizes.
  4. Cache is not included on the 4GB addressable space. Actually cache memory is not addressable at all. You can modify it indirectly but you cannot access it.

-----Mensaje original-----
De: xxxxx@lists.osr.com [mailto:xxxxx@lists.osr.com]En nombre de Kannan, Raja
Enviado el: lunes, 08 de agosto de 2005 12:47
Para: Windows System Software Devs Interest List
Asunto: [ntdev] Questions on TLB

Hello,
I want the answers to these following questions.

  1. Is TLB and level 1 & 2 caches are same?
  2. What is TLB thrashing?
  3. How many entries will be in TLB for code & data?
  4. In 32 bit windows OS , we can deploy 4GB of physical memory. This upper limit is including/excluding caches?

Can some one explain this in slightly greater detail. If you can refer me to some document as well related to this, it would help:

Thanks
-Raja

http: — Questions? First check the Kernel Driver FAQ at http://www.osronline.com/article.cfm?id=256 You are currently subscribed to ntdev as: unknown lmsubst tag argument: ‘’ To unsubscribe send a blank email to xxxxx@lists.osr.com

Questions? First check the Kernel Driver FAQ at http://www.osronline.com/article.cfm?id=256

You are currently subscribed to ntdev as: unknown lmsubst tag argument: ‘’
To unsubscribe send a blank email to xxxxx@lists.osr.com</http:>