pci mwi, cacheline and dma

Is it true that when I do dma from the local memory to the host memory, I
should not enable MWI? (thus the cacheline does not matter either)

I am running multiple boards (bus mastering) on win2k, but the performance
is not what I expected. I found out there is only 4-byte transaction on
PCI, and no burst ever. Why?

Thanks


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xxxxx@hotmail.com said:

Is it true that when I do dma from the local memory to the host
memory, I should not enable MWI?

You *should* use MWI. The cache line size is programmed into your
device config space if you need to do alignment, but the pages that
you get from allocators in kernel mode are aligned.

And besides, the only consequence is the page is flushed from the CACHE
on the host side, generally a *good* thing when you are writing from
a bus master:-)

xxxxx@hotmail.com said:

I found out there is only 4-byte transaction on PCI, and no burst
ever. Why?

Is your transaction being stopped? If so, the target is not accepting
the burst. If there is no STOP# yet you are deasserting IRDY# then
the board is not bursting. FIFOs?

Steve Williams “The woods are lovely, dark and deep.
xxxxx@icarus.com But I have promises to keep,
xxxxx@picturel.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep.”


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