I want to ask a question about the DMA contigouse buffer
if i allocated this buffer using the cache with size larger than the cache, what will happen??
and what is the limit to allocate from cache and is the performance of the system will be effected.?
thanks
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At 01:11 PM 2/1/2001 +0200, you wrote:
I want to ask a question about the DMA contigouse buffer
if i allocated this buffer using the cache with size larger than the
cache, what will happen??
and what is the limit to allocate from cache and is the performance of the
system will be effected.?
Allocating a contiguous buffer had no dependence on the processor L2 cache
size. PCI bus mastering on x86 systems does cache snooping, which keeps
memory coherent.
There is a potential performance impact if your PCI device doesn’t do
WRITE_INVALIDATE commands aligned on cache line boundaries (not the P4 has
a larger line size that the previous Intel processors). If you device does
do WRITE_INVALIDATE, lines in the cache will be discarded, on the
assumption the bus master will write a new version of the whole line to
RAM. If your device doesn’t do WRITE_INVALIDATE, the processor has to flush
the cache to RAM, usually BEFORE the bus master burst can execute. The hold
is often accomplished by inserting PCI wait states after the address phase
and before the target goes ready for the transfer. This increased latency
can be quite significant, and is highly dependent on the processor support
chipset (I’ve seen delays of like 15 PCI clocks while waiting for cache
writeback). If your PCI bursts are short, this added latency can cause your
average transfer performance to be really horrible (like 10 MBytes/sec, at
100% PIC bus utilization). Processor chipsets and PCI bridges can also
potentially buffer things, so the device thinks it wrote a burst to memory,
while the cache writeback is still in progress.
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