OSR PCI Sample Q.

NTDEV
1

Hi,
What is the purpose of calling “WriteIsDone” in the DPC
after wev’e already accumulated the bits in the ISR and
protected ourselves against another ISR served
before the execution of the DPC.

from which scenario do we protect ourselves
when using the synched “Read/WriteIsDone” ?

Thanks, Tom.

2

“Tomer Goldberg” wrote in message news:xxxxx@ntdev…
>
> What is the purpose of calling “WriteIsDone” in the DPC
> after wev’e already accumulated the bits in the ISR and
> protected ourselves against another ISR served
> before the execution of the DPC.
>

The “shadow copy” of the interrupt status register (where we accumulate the
bits) must be serialized against the ISR (where the bits are being
accouulated). Remember that we could have a read AND a write DMA in
progress simultaneously… but there’s only one “shadow copy” of the ISR
kept in the device extension…

peter
OSR

3

Ok, thats why we do this in the ISR:

devExt->IntCsr |= (intRegister & AMCC_INT_ACK_BITS);

this line solves the single shadow/multiple ISR’s.

but why do we need to sync with the ISR in the DPC:

KeSynchronizeExecution(devExt->InterruptObject,
WriteIsDone,
devExt)

after all in the DPC we already have the bits accumulated from the
ISR in case two ISR’s were
executed before the DPC had a chance.

-----Original Message-----
From: Peter Viscarola [mailto:xxxxx@osr.com]
Sent: Monday, July 01, 2002 5:33 PM
To: NT Developers Interest List
Subject: [ntdev] Re: OSR PCI Sample Q.

“Tomer Goldberg” wrote in message
> news:xxxxx@ntdev…
> >
> > What is the purpose of calling “WriteIsDone” in the DPC
> > after wev’e already accumulated the bits in the ISR and
> > protected ourselves against another ISR served
> > before the execution of the DPC.
> >
>
> The “shadow copy” of the interrupt status register (where we
> accumulate the
> bits) must be serialized against the ISR (where the bits are being
> accouulated). Remember that we could have a read AND a write DMA in
> progress simultaneously… but there’s only one “shadow copy”
> of the ISR
> kept in the device extension…
>
> peter
> OSR
>
>
>
>
> —
> You are currently subscribed to ntdev as: xxxxx@royatech.com
> To unsubscribe send a blank email to %%email.unsub%%
>

4

Thanks Peter,

ok, thats why we do this in the ISR:

devExt->IntCsr |= (intRegister & AMCC_INT_ACK_BITS);

this line solves the single shadow/multiple ISR’s.

but why do we need to sync with the ISR in the DPC:

KeSynchronizeExecution(devExt->InterruptObject,
WriteIsDone,
devExt)

after all in the DPC we already have the bits
accumulated from the ISR in case two ISR’s were
executed before the DPC had a chance.

-----Original Message-----
From: Peter Viscarola [mailto:xxxxx@osr.com]
Sent: Monday, July 01, 2002 5:33 PM
To: NT Developers Interest List
Subject: [ntdev] Re: OSR PCI Sample Q.

“Tomer Goldberg” wrote in message
> news:xxxxx@ntdev…
> >
> > What is the purpose of calling “WriteIsDone” in the DPC
> > after wev’e already accumulated the bits in the ISR and
> > protected ourselves against another ISR served
> > before the execution of the DPC.
> >
>
> The “shadow copy” of the interrupt status register (where we
> accumulate the
> bits) must be serialized against the ISR (where the bits are being
> accouulated). Remember that we could have a read AND a write DMA in
> progress simultaneously… but there’s only one “shadow copy”
> of the ISR
> kept in the device extension…
>
> peter
> OSR
>
>
>
>
> —
> You are currently subscribed to ntdev as: xxxxx@royatech.com
> To unsubscribe send a blank email to %%email.unsub%%
>

5

What happens if you shadow copy the bits in the ISR, and then use those
copied bits in the DPC, but after you checked your copy of the bits in the
DPC another interrupt came in? You will miss handling that interrupt until
a later interrupt comes in. Also, depending on how you clear the bits, you
could miss an interrupt altogether.

–
Bill McKenzie

“Tomer Goldberg” wrote in message news:xxxxx@ntdev…
>
>
> Thanks Peter,
>
> ok, thats why we do this in the ISR:
>
> devExt->IntCsr |= (intRegister & AMCC_INT_ACK_BITS);
>
> this line solves the single shadow/multiple ISR’s.
>
> but why do we need to sync with the ISR in the DPC:
>
> KeSynchronizeExecution(devExt->InterruptObject,
> WriteIsDone,
> devExt)
>
> after all in the DPC we already have the bits
> accumulated from the ISR in case two ISR’s were
> executed before the DPC had a chance.
>
>
> > -----Original Message-----
> > From: Peter Viscarola [mailto:xxxxx@osr.com]
> > Sent: Monday, July 01, 2002 5:33 PM
> > To: NT Developers Interest List
> > Subject: [ntdev] Re: OSR PCI Sample Q.
> >
> >
> >
> > “Tomer Goldberg” wrote in message
> > news:xxxxx@ntdev…
> > >
> > > What is the purpose of calling “WriteIsDone” in the DPC
> > > after wev’e already accumulated the bits in the ISR and
> > > protected ourselves against another ISR served
> > > before the execution of the DPC.
> > >
> >
> > The “shadow copy” of the interrupt status register (where we
> > accumulate the
> > bits) must be serialized against the ISR (where the bits are being
> > accouulated). Remember that we could have a read AND a write DMA in
> > progress simultaneously… but there’s only one “shadow copy”
> > of the ISR
> > kept in the device extension…
> >
> > peter
> > OSR
> >
> >
> >
> >
> > —
> > You are currently subscribed to ntdev as: xxxxx@royatech.com
> > To unsubscribe send a blank email to %%email.unsub%%
> >
>
>
>

6

Hmm, yes but as soon as you finish with your KeSynchronizeExecution-safe
processing of the same shadow bits they also can change due to another
interrupt. Perhaps the dpc routine needs to clear some of these bits?
That would be a good reason to use KeSynchronizeExecution.

-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com] On Behalf Of Bill McKenzie
Sent: Sunday, July 07, 2002 5:35 PM
To: NT Developers Interest List
Subject: [ntdev] Re: OSR PCI Sample Q.

What happens if you shadow copy the bits in the ISR, and then
use those copied bits in the DPC, but after you checked your
copy of the bits in the DPC another interrupt came in? You
will miss handling that interrupt until a later interrupt
comes in. Also, depending on how you clear the bits, you
could miss an interrupt altogether.

–
Bill McKenzie

“Tomer Goldberg” wrote in message
> news:xxxxx@ntdev…
> >
> >
> > Thanks Peter,
> >
> > ok, thats why we do this in the ISR:
> >
> > devExt->IntCsr |= (intRegister & AMCC_INT_ACK_BITS);
> >
> > this line solves the single shadow/multiple ISR’s.
> >
> > but why do we need to sync with the ISR in the DPC:
> >
> > KeSynchronizeExecution(devExt->InterruptObject,
> > WriteIsDone,
> > devExt)
> >
> > after all in the DPC we already have the bits
> > accumulated from the ISR in case two ISR’s were
> > executed before the DPC had a chance.
> >
> >
> > > -----Original Message-----
> > > From: Peter Viscarola [mailto:xxxxx@osr.com]
> > > Sent: Monday, July 01, 2002 5:33 PM
> > > To: NT Developers Interest List
> > > Subject: [ntdev] Re: OSR PCI Sample Q.
> > >
> > >
> > >
> > > “Tomer Goldberg” wrote in message
> > > news:xxxxx@ntdev…
> > > >
> > > > What is the purpose of calling “WriteIsDone” in the DPC after
> > > > wev’e already accumulated the bits in the ISR and protected
> > > > ourselves against another ISR served before the
> execution of the
> > > > DPC.
> > > >
> > >
> > > The “shadow copy” of the interrupt status register (where we
> > > accumulate the
> > > bits) must be serialized against the ISR (where the bits
> are being
> > > accouulated). Remember that we could have a read AND a
> write DMA in
> > > progress simultaneously… but there’s only one “shadow
> copy” of the
> > > ISR kept in the device extension…
> > >
> > > peter
> > > OSR
> > >
> > >
> > >
> > >
> > > —
> > > You are currently subscribed to ntdev as: xxxxx@royatech.com To
> > > unsubscribe send a blank email to %%email.unsub%%
> > >
> >
> >
> >
>
>
>
> —
> You are currently subscribed to ntdev as:
> xxxxx@hollistech.com To unsubscribe send a blank email to
> %%email.unsub%%
>