I perform a staged PCI (32bit) bus master DMA transfer under W2K on an Intel
platform with a page size of 4k.
I heard there are no map registers on Intel platforms. Therefore I expected
that DMA would take place in 4k stages. But during debugging I found that
there is a number of 2 map registers available on my test system (with
register base != NULL) and DMA is successfully performed in 8k stages.
What kind of mechanics implements map registers on Intel platforms? How does
it work?
Thanks in advance,
Volker Moebius
Basler AG
http://www.baslerweb.com
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Map registers on standard x86 platforms are implemented as non-paged pool
with a physical address less than 64MB. The OS allocates ‘map registers’ in
this region in physically contiguous chunks of 4K pages to support ISA(and
other) busses that cannot address the full 32-bit physical address space,
and to support non-scatter/gather busmaster devices even if they are on a
bus (e.g. pci) that does support the full 32-bit physical address space.
Data is simply copied in and out of the ‘map registers’ as part of the
kernels managed DMA support.
Other platforms may actually have hardware map registers (NT4 on Alpha.)
Mark Roddy
xxxxx@hollistech.com
www.hollistech.com
WindowsNT Windows 2000 Consulting Services
-----Original Message-----
From: Moebius, V. [mailto:xxxxx@baslerweb.com]
Sent: Tuesday, February 06, 2001 10:24 AM
To: NT Developers Interest List
Subject: [ntdev] Newbie question: What are map registers really …
I perform a staged PCI (32bit) bus master DMA transfer under
W2K on an Intel
platform with a page size of 4k.
I heard there are no map registers on Intel platforms.
Therefore I expected
that DMA would take place in 4k stages. But during debugging
I found that
there is a number of 2 map registers available on my test system (with
register base != NULL) and DMA is successfully performed in 8k stages.
What kind of mechanics implements map registers on Intel
platforms? How does
it work?
Thanks in advance,
Volker Moebius
Basler AG
http://www.baslerweb.com
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“Roddy, Mark” wrote in message news:xxxxx@ntdev…
>
> Map registers on standard x86 platforms are implemented as non-paged pool
> with a physical address less than 64MB. The OS allocates ‘map registers’
in
> this region in physically contiguous chunks of 4K pages to support ISA(and
> other) busses that cannot address the full 32-bit physical address space,
> and to support non-scatter/gather busmaster devices even if they are on a
> bus (e.g. pci) that does support the full 32-bit physical address space.
> Data is simply copied in and out of the ‘map registers’ as part of the
> kernels managed DMA support.
>
> Other platforms may actually have hardware map registers (NT4 on Alpha.)
>
Mark Roddy is, as usual, right on target with this answer. On small detail
is that that the map registers are in fact allocated below 16MB physical (in
A24 space) on systems with ISA buses.
It’s important to realize that Map Registers are also used on PAE-enabled
systems for support of 32-bit bus master DMA controllers (with or without
scatter/gather support) to allow these controllers to reach memory above the
32-bit (4GB) address mark. Buffers for this use, specifically, are located
anywhere below 4GB.
It’s all part of the HAL’s DMA abstraction.
Peter
OSR Open Systems Resources, Inc.
—
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> Mark Roddy is, as usual, right on target with this answer. On
small detail
is that that the map registers are in fact allocated below 16MB
physical (in
A24 space) on systems with ISA buses.
Peter
OSR Open Systems Resources, Inc.
Ah yes, the ‘on small detail’ done got me again 
Peter is of course
correct that the ridiculous ISA bus can’t even address 64MB, no it can only
address 16MB, and thus MAP registers are forced to be located below 16MB.
Yet Another Reason To Banish ISA Forever.
Mark Roddy
Windows 2000/NT Consultant
Hollis Technology Solutions
www.hollistech.com
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