Well, you can either know how the processor works, or, unless you’re
designing hardware, just ignore the whole thing about “how it works” and use
the appropriate functions that Windows supply, and blissfully ignore how it
actually works.
But yes, if the processor itself doesn’t support accesses that are different
for memory and IO, the PCI bridge will have a range of memory mapped
registers that translate into IO accesses on the PCI side of the bridge.
Using the windows functions will obviously make sure that any (PORT) IO
access is done to the IO range, and any (REGISTER) memory access through the
memory side of the PCI bridge.
–
Mats
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com]On Behalf Of CG
Sent: Tuesday, July 20, 2004 3:18 PM
To: Windows System Software Devs Interest List
Subject: Re: [ntdev] IO and memory address
Thanks I think it helps… I have the PCI book from Mindshare and I can see
that the PCI bridge prepares the transactions in order to specifiy if the
access is in the IO or memory space…
I understand that the CPU as mainly some I/O to designate to the PCI Bridge
if it’s an IO or memory access.
If the hardware (processor) doesn’t support IO access, the OS has to map IO
into memory space. So, the PCI bridge can know if this address is an access
to an IO or memory space. And it prepares the transactions for the target.
So, the main point is to know how the processor works with the whole
system…
Best regards
Christian
----- Original Message -----
From: xxxxx@3Dlabs.com mailto:xxxxx
To: Windows System Software Devs Interest mailto:xxxxx List
Sent: Tuesday, July 20, 2004 9:53 AM
Subject: RE: [ntdev] IO and memory address
Christian,
This does depend on the hardware your platform is based on.
On a standard x86 based PC: No, IO address 8000 and Memory address 8000 are
quite different. More below.
On a non-x86 based platform, such as Itanium or Motorola 68000: IO address
8000 will probably not match memory access to 0x8000, but it may be the same
as memory access of +0x8000.
The difference between x86 (and some releated products) and other
architectures is that it’s got a pin (or set of pins) that indicate if
something is a Memory or IO access. Most other processors just map some
memory range to be the “IO space”, and the rest is “memory”. How this is
done depends very much on the particular platform. For instance, it was very
popular to use bit 31 to indicate “IO”, because it’s trivial to decode. Of
course, in a modern system where 2GB of RAM isn’t entirely unlikely, this
isn’t very practical. So more complex decoding principles have been
constructed.
In x86, there is a particular set of instructions to indicate “IO” access.
These are IN/OUT/INS/OUTS, with varying sizes for the operand (8, 16, 32 and
64 bits if we include x86-64). So if you look at the assembly code for a
write to IO address 0x8000:
mov dx, 0x8000
mov al, 0x42
out dx, al
While a memory access would look like:
mov edx, 0x8000
mov al, 0x42
mov [edx], al
Note also that the IO space is limited to 64KB of address space, so it’s not
as large as the memory space.
In the driver, you’d want to use WRITE_PORT_XXXX (e.g. WRITE_PORT_UCHAR) to
do a IO access, and WRITE_REGISTER_XXXX to do a MEMORY type access. But you
can also use pointers to access a memory based device, such as:
unsigned char *ptr;
ptr = (unsigned char *)0x8000;
*ptr = 0x42;
As to how this translates to the hardware: I described that there is a pin
on the x86 processor to indicate I/O or Memory. This is then translated to
the PCI bus (for instance) to again indicate which type of access is
intended.
It’s fairly common these days to have hardware registers mapped as memory
ranges as well as I/O registers. Many PCI devices (especially ones that
aren’t specifically targeted at x86) use memory mapped IO registers. On a
PnP based hardware, the PCI enumerator (in the BIOS or in Windows) will dole
out suitable ranges of memory to the different base addresses of the device,
and so all you need to do is figure out from the “BAR” (Base Address
Register) in the PCI config space what you’ve been given and go out and
access the memory.
Hope this helps. If you have specific questions, let us know…
–
Mats
-----Original Message-----
From: xxxxx@lists.osr.com
[mailto:xxxxx@lists.osr.com]On Behalf Of CG
Sent: Tuesday, July 20, 2004 2:24 PM
To: Windows System Software Devs Interest List
Subject: [ntdev] IO and memory address
Hello,
I would like to know the difference between the IO and memory access to the
peripheral at hardware level. Does the processor use a specific interface
to access to IO or memory access?
For example, if I access to the IO 0x8000… so, the memory access 0x8000 is
it the same?
In brief, I would like to understand this difference please.
Best regards
Christian
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