I have the following scenario.
Windows NT
single port NIC, dual processor system.
The InterruptObject for my single port NIC does not have affinity
to either processor.
In this case does Windows NT/XP/ 2K do any interrupt balancing,
if at all ?
Is there any such thing as a soft affinity for the interrupts to a
particular processor ?
Any pointers / advice would be greatly appreciated.
Thanks,
-Shilpa
If your hardware platform supports it, w2k will use the IOAPIC/APIC bus
to route interrupts to the most available processor.
You can specify an interrupt affinity when you connect interrupts, but
this is a hard affinity not a soft affinity.
The decision by the IOAPIC/APIC interrupt mechanism about which cpu is
the ‘most available’ includes, if I remember correctly, some knowledge
about which cpu last serviced this interrupt vector, and, all other
factors being equal, will choose the same processor again. This
qualifies as a soft affinity.
===========================
Mark Roddy
Consultant, Microsoft DDK MVP
Hollis Technology Solutions
xxxxx@hollistech.com
www.hollistech.com
603-321-1032
-----Original Message-----
From: xxxxx@nai.com
To: “NT Developers Interest List”
Date: Wed, 18 Sep 2002 13:26:38 -0400
Subject: [ntdev] Interrupt affinity on SMP systems
> I have the following scenario.
> Windows NT
> single port NIC, dual processor system.
>
> The InterruptObject for my single port NIC does not have affinity
> to either processor.
>
> In this case does Windows NT/XP/ 2K do any interrupt balancing,
> if at all ?
>
> Is there any such thing as a soft affinity for the interrupts to a
> particular processor ?
>
> Any pointers / advice would be greatly appreciated.
>
> Thanks,
> -Shilpa
>
> —
> You are currently subscribed to ntdev as: xxxxx@hollistech.com
> To unsubscribe send a blank email to %%email.unsub%%
On P-III or early processosr, the interrupt can be delivered by IOAPIC to a
particular processor or to any processor, depending on how you program the
IOAPIC through a 3-wire APIC bus. In case it is broadcasted on APIC bus, the
current APIC ID of Local APICs will be used for APIC bus arbitration, the
higher APIC ID, the higher priority. Winner’s APIC ID is reduced to 0 and
loser’s ID get incremented. This actually becomes a round-robin scheme.
On P-IV, xAPIC uses FSB to deliver the interrupt (interrupt becomes a bus
protocol message), one can still program IOAPIC to deliever interrupt to
specific processor. Otherwise, whoever (processor) claim the FSB gets the
interrupt.
See Intel System Programmer Ref Chapt 8.
-----Original Message-----
From: Mark Roddy [mailto:xxxxx@hollistech.com]
Sent: Wednesday, September 18, 2002 1:03 PM
To: NT Developers Interest List
Subject: [ntdev] Re: Interrupt affinity on SMP systems
If your hardware platform supports it, w2k will use the IOAPIC/APIC bus
to route interrupts to the most available processor.
You can specify an interrupt affinity when you connect interrupts, but
this is a hard affinity not a soft affinity.
The decision by the IOAPIC/APIC interrupt mechanism about which cpu is
the ‘most available’ includes, if I remember correctly, some knowledge
about which cpu last serviced this interrupt vector, and, all other
factors being equal, will choose the same processor again. This
qualifies as a soft affinity.
===========================
Mark Roddy
Consultant, Microsoft DDK MVP
Hollis Technology Solutions
xxxxx@hollistech.com
www.hollistech.com
603-321-1032
-----Original Message-----
From: xxxxx@nai.com
To: “NT Developers Interest List”
Date: Wed, 18 Sep 2002 13:26:38 -0400
Subject: [ntdev] Interrupt affinity on SMP systems
> I have the following scenario.
> Windows NT
> single port NIC, dual processor system.
>
> The InterruptObject for my single port NIC does not have affinity
> to either processor.
>
> In this case does Windows NT/XP/ 2K do any interrupt balancing,
> if at all ?
>
> Is there any such thing as a soft affinity for the interrupts to a
> particular processor ?
>
> Any pointers / advice would be greatly appreciated.
>
> Thanks,
> -Shilpa
>
> —
> You are currently subscribed to ntdev as: xxxxx@hollistech.com
> To unsubscribe send a blank email to %%email.unsub%%
—
You are currently subscribed to ntdev as: xxxxx@appstream.com
To unsubscribe send a blank email to %%email.unsub%%
RE: [ntdev] Re: Interrupt affinity on SMP systems+ Priority Arbitration
----- Original Message -----
From: Bi Chen
To: NT Developers Interest List
Sent: Wednesday, September 18, 2002 11:36 PM
Subject: [ntdev] Re: Interrupt affinity on SMP systems
On P-III or early processosr, the interrupt can be delivered by IOAPIC to a particular processor or to any processor, depending on how you program the IOAPIC through a 3-wire APIC bus. In case it is broadcasted on APIC bus, the current APIC ID of Local APICs will be used for APIC bus arbitration, the higher APIC ID, the higher priority. Winner’s APIC ID is reduced to 0 and loser’s ID get incremented. This actually becomes a round-robin scheme.
On P-IV, xAPIC uses FSB to deliver the interrupt (interrupt becomes a bus protocol message), one can still program IOAPIC to deliever interrupt to specific processor. Otherwise, whoever (processor) claim the FSB gets the interrupt.
See Intel System Programmer Ref Chapt 8.
-----Original Message-----
From: Mark Roddy [mailto:xxxxx@hollistech.com]
Sent: Wednesday, September 18, 2002 1:03 PM
To: NT Developers Interest List
Subject: [ntdev] Re: Interrupt affinity on SMP systems
If your hardware platform supports it, w2k will use the IOAPIC/APIC bus
to route interrupts to the most available processor.
You can specify an interrupt affinity when you connect interrupts, but
this is a hard affinity not a soft affinity.
The decision by the IOAPIC/APIC interrupt mechanism about which cpu is
the ‘most available’ includes, if I remember correctly, some knowledge
about which cpu last serviced this interrupt vector, and, all other
factors being equal, will choose the same processor again. This
qualifies as a soft affinity.
===========================
Mark Roddy
Consultant, Microsoft DDK MVP
Hollis Technology Solutions
xxxxx@hollistech.com
www.hollistech.com
603-321-1032
-----Original Message-----
From: xxxxx@nai.com
To: “NT Developers Interest List”
Date: Wed, 18 Sep 2002 13:26:38 -0400
Subject: [ntdev] Interrupt affinity on SMP systems
> I have the following scenario.
> Windows NT
> single port NIC, dual processor system.
>
> The InterruptObject for my single port NIC does not have affinity
> to either processor.
>
> In this case does Windows NT/XP/ 2K do any interrupt balancing,
> if at all ?
>
> Is there any such thing as a soft affinity for the interrupts to a
> particular processor ?
>
> Any pointers / advice would be greatly appreciated.
>
> Thanks,
> -Shilpa
>
> —
> You are currently subscribed to ntdev as: xxxxx@hollistech.com
> To unsubscribe send a blank email to %%email.unsub%%
—
You are currently subscribed to ntdev as: xxxxx@appstream.com
To unsubscribe send a blank email to %%email.unsub%%
—
You are currently subscribed to ntdev as: xxxxx@rdsor.ro
To unsubscribe send a blank email to %%email.unsub%%
RE: [ntdev] Re: Interrupt affinity on SMP systemsAt high interrupt rates, this tends to suck pretty badly. For example, if you
get two interrupts quickly from the same device, the first one gets taken by say CPU 3 which ACKs it in the ISR, then does the
rest of the ISR, and the second one gets taken by CPU4, which immediately gets stuck on the interrupt spin lock for that device
because CPU 3 is still in the ISR.
If your ISR is faster than than the interrupt turn around time, every interrupt tends to have to drag all the cache associated
with the device to the CPU that services it.
If you have a device that generates lots of interrupts, you are probably better off setting some affinity to a single CPU. Of
course ScsiPort (and probably NDIS) would connect the interrupts for you, not giving you any way to specify affinity w/o a
proprietary HAL.
-DH
“Bi Chen” wrote in message news:xxxxx@ntdev…
On P-III or early processosr, the interrupt can be delivered by IOAPIC to a particular processor or to any processor, depending
on how you program the IOAPIC through a 3-wire APIC bus. In case it is broadcasted on APIC bus, the current APIC ID of Local
APICs will be used for APIC bus arbitration, the higher APIC ID, the higher priority. Winner’s APIC ID is reduced to 0 and
loser’s ID get incremented. This actually becomes a round-robin scheme.
On P-IV, xAPIC uses FSB to deliver the interrupt (interrupt becomes a bus protocol message), one can still program IOAPIC to
deliever interrupt to specific processor. Otherwise, whoever (processor) claim the FSB gets the interrupt.
See Intel System Programmer Ref Chapt 8.
-----Original Message-----
From: Mark Roddy [mailto:xxxxx@hollistech.com]
Sent: Wednesday, September 18, 2002 1:03 PM
To: NT Developers Interest List
Subject: [ntdev] Re: Interrupt affinity on SMP systems
If your hardware platform supports it, w2k will use the IOAPIC/APIC bus
to route interrupts to the most available processor.
You can specify an interrupt affinity when you connect interrupts, but
this is a hard affinity not a soft affinity.
The decision by the IOAPIC/APIC interrupt mechanism about which cpu is
the ‘most available’ includes, if I remember correctly, some knowledge
about which cpu last serviced this interrupt vector, and, all other
factors being equal, will choose the same processor again. This
qualifies as a soft affinity.
===========================
Mark Roddy
Consultant, Microsoft DDK MVP
Hollis Technology Solutions
xxxxx@hollistech.com
www.hollistech.com
603-321-1032
-----Original Message-----
From: xxxxx@nai.com
To: “NT Developers Interest List”
Date: Wed, 18 Sep 2002 13:26:38 -0400
Subject: [ntdev] Interrupt affinity on SMP systems
> I have the following scenario.
> Windows NT
> single port NIC, dual processor system.
>
> The InterruptObject for my single port NIC does not have affinity
> to either processor.
>
> In this case does Windows NT/XP/ 2K do any interrupt balancing,
> if at all ?
>
> Is there any such thing as a soft affinity for the interrupts to a
> particular processor ?
>
> Any pointers / advice would be greatly appreciated.
>
> Thanks,
> -Shilpa
>
> —
> You are currently subscribed to ntdev as: xxxxx@hollistech.com
> To unsubscribe send a blank email to %%email.unsub%%
—
You are currently subscribed to ntdev as: xxxxx@appstream.com
To unsubscribe send a blank email to %%email.unsub%%
Hi, Dave:
Great Observation. However, I would add if the hardware generates lot of
interrupt in short interval, I would go back to hardware guys and ask them
to take look at I2O spec. and do similar thing. I used have a lot of fun to
program drivers for hardware using Intel I960Rx IO processor as embedded
controller and PCI interface. General purpose CPU like IA32 family sucks in
terms of handling interrupt (not PowerPC though).
Bi
-----Original Message-----
From: Dave Harvey [mailto:xxxxx@syssoftsol.com]
Sent: Wednesday, September 25, 2002 9:12 PM
To: NT Developers Interest List
Subject: [ntdev] Re: Interrupt affinity on SMP systems
RE: [ntdev] Re: Interrupt affinity on SMP systemsAt high interrupt rates,
this tends to suck pretty badly. For example, if you
get two interrupts quickly from the same device, the first one gets taken by
say CPU 3 which ACKs it in the ISR, then does the
rest of the ISR, and the second one gets taken by CPU4, which immediately
gets stuck on the interrupt spin lock for that device
because CPU 3 is still in the ISR.
If your ISR is faster than than the interrupt turn around time, every
interrupt tends to have to drag all the cache associated
with the device to the CPU that services it.
If you have a device that generates lots of interrupts, you are probably
better off setting some affinity to a single CPU. Of
course ScsiPort (and probably NDIS) would connect the interrupts for you,
not giving you any way to specify affinity w/o a
proprietary HAL.
-DH
“Bi Chen” wrote in message news:xxxxx@ntdev…
On P-III or early processosr, the interrupt can be delivered by IOAPIC to a
particular processor or to any processor, depending
on how you program the IOAPIC through a 3-wire APIC bus. In case it is
broadcasted on APIC bus, the current APIC ID of Local
APICs will be used for APIC bus arbitration, the higher APIC ID, the higher
priority. Winner’s APIC ID is reduced to 0 and
loser’s ID get incremented. This actually becomes a round-robin scheme.
On P-IV, xAPIC uses FSB to deliver the interrupt (interrupt becomes a bus
protocol message), one can still program IOAPIC to
deliever interrupt to specific processor. Otherwise, whoever (processor)
claim the FSB gets the interrupt.
See Intel System Programmer Ref Chapt 8.
-----Original Message-----
From: Mark Roddy [mailto:xxxxx@hollistech.com]
Sent: Wednesday, September 18, 2002 1:03 PM
To: NT Developers Interest List
Subject: [ntdev] Re: Interrupt affinity on SMP systems
If your hardware platform supports it, w2k will use the IOAPIC/APIC bus
to route interrupts to the most available processor.
You can specify an interrupt affinity when you connect interrupts, but
this is a hard affinity not a soft affinity.
The decision by the IOAPIC/APIC interrupt mechanism about which cpu is
the ‘most available’ includes, if I remember correctly, some knowledge
about which cpu last serviced this interrupt vector, and, all other
factors being equal, will choose the same processor again. This
qualifies as a soft affinity.
===========================
Mark Roddy
Consultant, Microsoft DDK MVP
Hollis Technology Solutions
xxxxx@hollistech.com
www.hollistech.com
603-321-1032
-----Original Message-----
From: xxxxx@nai.com
To: “NT Developers Interest List”
Date: Wed, 18 Sep 2002 13:26:38 -0400
Subject: [ntdev] Interrupt affinity on SMP systems
> I have the following scenario.
> Windows NT
> single port NIC, dual processor system.
>
> The InterruptObject for my single port NIC does not have affinity
> to either processor.
>
> In this case does Windows NT/XP/ 2K do any interrupt balancing,
> if at all ?
>
> Is there any such thing as a soft affinity for the interrupts to a
> particular processor ?
>
> Any pointers / advice would be greatly appreciated.
>
> Thanks,
> -Shilpa
>
> —
> You are currently subscribed to ntdev as: xxxxx@hollistech.com
> To unsubscribe send a blank email to %%email.unsub%%
—
You are currently subscribed to ntdev as: xxxxx@appstream.com
To unsubscribe send a blank email to %%email.unsub%%
—
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