Actually, HyperTransport does have the necessary mechanisms for
acknowledging level-triggered interrupts. If you’re seeing a problem
with this on a HyperTransport system, it’s a chipset bug, not a feature
of the bus. (Which chipset are you using?)
Jake Oshins
Windows Kernel Team
-----Original Message-----
Subject: Re: ISR and multiple processor system issue
From: Bi Chen
Date: Thu, 19 Sep 2002 14:52:56 -0700
X-Message-Number: 25
I’ve seen some odd Video hardware use edge trigged interrupt for
vertical
blanking interval. I agree with you the hardware design may not follow
normal practice, that is using level-sensitive interrupt (on PCI) or
shadow
interrupt status register. Another interesting point, HyperTransport
(AMD)
cannot express leveled interrupt because interrupt is delivered through
packetized message. The Local APIC cannot buffer this message if the
vector
has a pending interrupt. IOAPIC does not know if the message is lost and
so
it does not resending the message. This is not a problem if the device
is
single function device or multifunction devices that do not share the
same
interrupt vector. I believe this is true at least for spec 1.1. Correct
me
if I am wrong.
Bi