Hello everybody!
There is an a PCI busmaster high speed analog-to-digital converter (ADC).
Its working sampling frequency is about 40MHz. It provides to driver
writer a few ports. To be simple, let’s say:
- 1st: start memory address port
- 2nd: stop memory address port
- 3d : start/stop device port (1 - Start, 0 - Stop)
Device operates only with a block of *physical* *contiguous* memory.
To start the device we have to allocate physical contiguous block of
memory: let it be lpData and dwLength - variables which are responsible
for the pointer to physical memory block and the size of an allocated
block respectively.
Fill the 1st & 2nd device ports with the and values. Write to the 3d
port 1 (start the device).
dwLength-bytes memory block will be filled up with data for about
dwLength/40000000 seconds. For instance:
1Mb - 26 milliseconds
10Mb - 260 milliseconds.
After the block filled device generates an interrupt. Here the driver
should have time to insert another block of memory while the user
application processes the first one (some kind of circular buffer).
This all should be processed in a real-time (probably on multiprocessor
system).
I’ve read the NT Device Driver book by Art Baker but a little bit confused
on a few subjects:
1. If it is possible to allocate a huge number of physical contiguous
memory mapped to the user space ?
//
// Also it seems to have scatter/gather support:
// if the 1st port while device started will be loaded with another
// block address the device after interrupting will automatically start
// transferring data to this second memory address (no more then 2
// addresses) – or I am wrong in terminology of ‘scatter-gather’ ?
//
2. What the driver should rely on ?
//
// Coomon-buffer busmaster DMA driver:
// HalGetAdapter + HalAllocateCommonBuffer
//
// Paccket-based busmaster DMA driver:
// HalGetAdapter + IoMapTransfer
//
Could anyone please help me to understand those subjects.
(Dont forget plz about speed and milliseconds :))
If it is necessary I also can ask hardware developers to fix their ADC a
little (FIFO buffer enlargement, interrupt issues, more ports and extra
funcionalities, etc.)
Really sorry for a long message…
Thanks in advance
–
Best regards,
Dmitry Potapenko mailto:xxxxx@jeo.ru
> Its working sampling frequency is about 40MHz. It provides to driver
writer a few ports. To be simple, let’s say:
- 1st: start memory address port
- 2nd: stop memory address port
- 3d : start/stop device port (1 - Start, 0 - Stop)
Device operates only with a block of *physical* *contiguous* memory.
Call ->GetScatterGatherList or ->MapTransfer in a loop.
Program the hardware for a physically contiguous chunk of your IRP.
Then move to the next chunk on an interrupt.
The interrupt rate you need is 10kHz, provided the sample is 1 byte.
Can work. Otherwise, the hardware will require scatter-gather-list
support - like IDE or USB does this.
Max
Hey, Max!
Thank you. I’ve already thought no one would answer…
DP>> Its working sampling frequency is about 40MHz.
[skipped]
DP>> Device operates only with a block of *physical* *contiguous* memory.
M> Call ->GetScatterGatherList or ->MapTransfer in a loop.
M> Program the hardware for a physically contiguous chunk of your IRP.
M> Then move to the next chunk on an interrupt.
Sorry-sorry, forgot to say – driver should work under NT40 (SP5)
“GetScatterGatherList” and “MapTransfer” are supposed to be absolute, is
it right to use IoMapTransfer on NT and what is the equivalent here for
“GetScatterGatherList” ?
M> The interrupt rate you need is 10kHz, provided the sample is 1 byte.
M> Can work.
You’re talking about the 4Kb buffers (pages). Ok, that buffer would be
filled up for about 1/10kHz = 0.1 ms. So, each 100 microseconds we will
serve the interrupt. How would it effect to the system performance and
would it overwhelm the kernel’s interrupt dispatcher or not?
(I maybe mistaken but I think it would overwhelm – show me if I am wrong)
M> Otherwise, the hardware will require scatter-gather-list support
^^^^^^^^^^^^^^^^^^^
Tell me plz what is that mean ? What hardware should be to have a
“scatter-gather-list” – I’ve already said that I could ask hardware
developers to correct their device a little…
Thanx for your answers.
P.S. I’ve written about dozen of drivers but more then half of them were
almost the same. That’s why I think I am a bit a newcomer 
So plz be
more detailed.
–
Best regards,
Dmitry Potapenko mailto:xxxxx@jeo.ru
> Sorry-sorry, forgot to say – driver should work under NT40 (SP5)
“GetScatterGatherList” and “MapTransfer” are supposed to be
absolute, is
it right to use IoMapTransfer on NT
Yes. You can also use IoMapTransfer on w2k/XP, where it is a synonim
for ->MapTransfer.
filled up for about 1/10kHz = 0.1 ms. So, each 100 microseconds we
will
serve the interrupt. How would it effect to the system performance
and
Normally. 10K interrupts per second. A modem together with some other
stuff cannot saturate Pentium III with thousand of interrupts.
M> Otherwise, the hardware will require scatter-gather-list support
^^^^^^^^^^^^^^^^^^^
Tell me plz what is that mean ?
A page of pointers to real data pages. Like IDE uses. The hardware
then fetches the data pointers, knowing only the base address of the
index page. No more per-page interrupts. This is the simplest form of
the chain DMA (aka hardware scatter-gather lists). See the OHCI1394
spec for more smart one.
Max
Wed, 4 Jun 2003 11:57:37 +0400
“Maxim S. Shatskih” wrote:
Sorry for separating the thread. I’ve thought it was already not a good
idea to list more then a half of messages to get to the original thread.
Moreover if it is not fitted on the screen…
MS>>> Otherwise, the hardware will require scatter-gather-list support
DP>> ^^^^^^^^^^^^^^^^^^^
MS> A page of pointers to real data pages. Like IDE uses. The hardware
MS> then fetches the data pointers, knowing only the base address of the
MS> index page.
… and the number of data pointers (aka descriptors)
MS> No more per-page interrupts. This is the simplest form of
MS> the chain DMA (aka hardware scatter-gather lists). See the OHCI1394
MS> spec for more smart one.
“1394 Open Host Controller Interface Specification Release 1.1”
ftp://download.intel.com/technology/1394/download/ohci_11.pdf [2 368 498]
I’ve got your point. It’s described in details in Chapter 3:
Common DMA Controller Feature
So, what if that PCI-adc would have a FIFO (= page of pointers) ?
Software should load (push) some number of valid pointers into that FIFO
and then start the transfer.
[I] Hardware would pop the pointer from a FIFO and process data transfer
with that pointer while the FIFO is not empty. When it gets empty - we get
an interrupt from a device. Also new pointers could be added while device
processing with data transfer.
OR (more reliable variant)
[II] Hardware in a cycle for i: 0%N-1 gets the pointer[i] and processes
transfer. When the N-th pointer has been processed - we recieve an IRQ.
And the device (optionally) starts from the beginning with the pointer[0]
Is it an implementation of a scatter-gather support ? Do you think it
worth demanding the hardware developers to fix a little the design of
an a device ?
> Is it an implementation of a scatter-gather support ?
Yes. The general idea is that the list of pages is somewhere in the
memory, and the hardware accesses this list itself.
Do you think it
worth demanding the hardware developers to fix a little the design
of
an a device ?
Yes. For high-speed device (like OHCI1394), this is a must. Otherwise
nobody will guarantee you the interrupt latency you will need.
BTW - aic78xx is a very old hardware, but uses the similar stuff. Look
at FreeBSD driver for it.
Max
Thank you, Maxim! I do appriciate your help.
–
Best regards,
Dmitry Potapenko