> Believe me, there’s life outside the OS!
Yes, there is. But the case you’ve picked is particularly grusome to try to
solve. Even quite ignoring that probably most OSes would get upset with the
kind of poing around you would have to do, or would prevent you from doing
some of it, there is the problem that the hardware itself might get upset,
and you will end up creating a mess that didn’t exist before you started
poking.
Your first big problem is going to be finding the busses. About the only
way you can do this reliably is to get your hands on the ACPI tables, run an
ACPI interpreter, walk the tree, and find the host bridge addresses.
Now you have the problem of dealing with the host bridges. You *do* know
how to deal with a UNO035 host bridge, don’t you? And you know the rather
major and critical differences between it and a UNO030? Oh wait, I forgot.
We don’t publish the specs on those bridges since only my HALs and the BIOS
and ASL code really need to deal with them, plus some of our proprietary
drivers.
Well, once you get the host bridges set up right and the IO and bus memory
mapped, you can start walking down the PCI busses outside them to see what
is there. It is important that you do this in the right order though,
otherwise you might not end up with IO space mapped for the compatability
board, and none of the standard peripherals will work any more.
If you look in the bridge spec (that we don’t publish) you will see some
flags you need to look at to do this right. Oh, the algorithms aren’t in
the spec. And it doesn’t really mention there which flags you need to look
at to do this right. That was all figured out by the BIOS group after the
hardware group wrote the spec, and the hardware group doesn’t figure those
sort of details belong in their spec.
Now, that’s just to deal with the host bridges on a couple of Unisys
machines I happen to know about off the top of my head. I’d be willing to
bet that there are a bunch of equally interesting things out there that I
don’t know about, but other iron vendors do.
And all of that is completely ignoring systems that don’t map bus memory
space 1:1 into host memory space, or that use indirection registers to get
to the PCI config space for the busses in other clusters and the like.
Loren